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data sheet rev. 3.1 / july 2012 sap5s / sap51 universal actuator-sensor interface ic
sap5s / sap51 universal actuator-sensor interface ic ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. brief description sap5s/sap51 is a new generation cmos integrated circuit for as-i networks. the low-level field bus as-i (actuator sensor interface) was designed for easy, safe and cost- effective interconnection of sensors, actuators and switches. it transports both power and data over the same two-wire unshielded cable. sap5s/sap51 is used as a part of a master or slave node and works as an interface to the physical bus. the device realizes power supply, physical data transfer and communication protocol handling and is fully compliant with as-interface complete specification v3.0. sap5s/sap51 can be programm ed by the user to operate in standard slave mode, safety mode sap5s only) or master mode. the special as-i safety mode (sap5s only) assures short response times regarding security related events. all configuration data are stored in an internal eeprom that can be easily programmed by a stationary or handheld programming device. sap5s / sap51 is optimized for harsh environments by it?s special burst protection circuitry and excellent electromagnetic compatibility. features ? compliant with asi complete specification v3.0 ? integrated safety code generator (sap5s only) ? universal application: in slaves, masters, repeaters and bus-monitors ? on-chip electronic inductor: 55 ma current drive capability ? two led outputs to support spec. v3.0 status indication modes ? user programmable to operation in standard slave mode, safety mode or master mode ? supports 5.33/16 mhz cr ystals by automatic frequency detection ? data pre-processing functions ? special burst protection circuitry ? excellent electromagnetic compatibility ? clock and communication watchdogs for high system security benefits ? cost savings due to integrated safety code generator (sap5s) ? functional and pin compatible to sap4.1 ? automatic x-tal detection (5,3333mhz or 16,0000mhz) ? supports as-i complete specification 3.0 available support ? zmdi as-interface programmer kit usb ? zmdi sap5 evaluation board v2.0 physical characteristics ? operational temperature range: -25 to +85c ? sop16 and sop20 package sap5s/sap51 basic a pplication circuit +24v +0v asi+ asi- asi+ asi- sap5s u5r cdc ltpn ltgp osc2 osc1 uin uout d2 d0 d1 d3 standard application safety mode slave application sap51/ sap5s u5r cdc ltpn ltgp osc2 osc1 uin uout pfault d0...3 dstbn p0...3 led2 led1 pstbn
sap5s / sap51 universal actuator-sensor interface ic ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. typical applications ? as-i master modules ? as-i slave modules ? as-i safety modules (sap5s only) sap5s/sap51 block diagram ordering information ordering code operating temperature range package type rohs conform packaging minimum order quantity sap5sd-a-g1-t sap51d-a-g1-t -25c to +85c sop20 / 300 mil y tubes (37 parts/tube) 370 pcs. (10 tubes) sap5sd-a-g1-r SAP51D-A-G1-R -25c to +85c sop20 / 300 mil y tape & reel (1000 parts/reel) 1000 pcs. (one reel) sap5sd-b-g1-t sap51d-b-g1-t -25c to +85c sop16 / 300 mil y tubes (46 parts/tube) 460 pcs. (10 tubes) sap5sd-b-g1-r sap51d-b-g1-r -25c to +85c sop16 / 300 mil y tape & reel (1000 parts/reel) 1000 pcs. (one reel) sales and further information www.zmdi.com asi@zmdi.com zentrum mikroelektronik dresden ag grenzstrasse 28 01109 dresden germany zmd america, inc. 1525 mccarthy blvd., #212 milpitas, ca 95035-7453 usa zentrum mikroelektronik dresden ag, japan office 2nd floor, shinbashi tokyu bldg. 4-21-3, shinbashi, minato-ku tokyo, 105-0004 japan zmd far east, ltd. 3f, no. 51, sec. 2, keelung road 11052 taipei taiwan zentrum mikroelektronik dresden ag, korean office posco centre building west tower, 11th floor 892 daechi, 4-dong, kangnam-gu seoul, 135-777 korea phone +49.351.8822.7274 fax +49.351.8822.87274 phone +855-ask-zmdi (+855.275.9634) phone +81.3.6895.7410 fax +81.3.6895.7301 phone +886.2.2377.8189 fax +886.2.2377.8199 phone +82.2.559.0660 fax +82.2.559.0700 disclaimer : this information applies to a product under development. its characteristics and specifications are subject to change without notice. zentrum mikroelektronik dresden ag (zmd ag) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. the information furnished hereby is believed to be true and accurate. however, under no circumstances shall zmd ag be liable to any customer, licensee, or any other third party for any special, ind irect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. zmd ag hereby expressly disclaims any liability of zmd ag to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any li ability of zmd ag for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (includi ng negligence), strict liability, or otherwise.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 4 of 62 contents 0 ? read this first ................................................................................................................ ............................... 8 ? 0.1. ? important notice ..................................................................................................................................... 8 ? 0.2. ? references ............................................................................................................................................. 8 ? 0.3. ? revision hi story............................................................................................................... ....................... 8 ? 1 ? general device specification ................................................................................................... ..................... 9 ? 1.1. ? absolute maximum rati ngs (non op erating)....................................................................................... .. 9 ? 1.2. ? operating co nditions ........................................................................................................... ................. 10 ? 1.3. ? emc behav ior................................................................................................................... .................... 10 ? 1.4. ? quality standards .............................................................................................................. ................... 10 ? 1.5. ? failure rate ................................................................................................................... ....................... 11 ? 1.6. ? humidity class................................................................................................................. ..................... 11 ? 1.7. ? package pin a ssignme nt......................................................................................................... ............. 12 ? 2 ? basic functional description ................................................................................................... .................... 14 ? 2.1. ? functional bl ock diagram....................................................................................................... .............. 14 ? 2.2. ? general operat ional modes ...................................................................................................... ........... 16 ? 2.3. ? slave mode..................................................................................................................... ...................... 16 ? 2.3.1. ? as-i communicati on channel ..................................................................................................... .... 16 ? 2.3.2. ? parameter po rt pins............................................................................................................ ........... 16 ? 2.3.3. ? data port pins ................................................................................................................. ............... 17 ? 2.3.4. ? data input inversion ........................................................................................................... ............ 17 ? 2.3.5. ? data input filtering........................................................................................................... .............. 17 ? 2.3.6. ? synchronous da ta i/o mode...................................................................................................... .... 17 ? 2.3.7. ? 4 input / 4 output processing in extended address m ode ............................................................ 17 ? 2.3.8. ? as-i safety mode ............................................................................................................... ............ 18 ? 2.3.9. ? enhanced led status indi cation ................................................................................................. .. 18 ? 2.3.10. ? communication moni tor/watchdog................................................................................................ 1 8 ? 2.3.11. ? write protection of id _code_extension_1..................................................................................... 18 ? 2.3.12. ? summary of ma ster calls........................................................................................................ ....... 19 ? 3 ? e2prom ......................................................................................................................... ............................. 22 ? 3.1. ? overview....................................................................................................................... ........................ 22 ? 3.2. ? user area progra mming.......................................................................................................... ............. 23 ? 3.3. ? firmware area progra mming ...................................................................................................... ......... 25 ? 3.4. ? safety area programming ........................................................................................................ ............ 26 ? 4 ? detailed functional description................................................................................................ ................... 28 ? 4.1. ? power s upply................................................................................................................... ..................... 28 ? 4.1.1. ? voltage output pins uout and u5r............................................................................................. 28 ? 4.1.2. ? input impedance (a s-i bus load) ................................................................................................ ... 29 ? 4.2. ? thermal pr otecti on ............................................................................................................. .................. 29 ?
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 5 of 62 4.3. ? dc characteristics ? digital inputs............................................................................................ ........... 30 ? 4.4. ? dc characteristics ? digital outputs ........................................................................................... ......... 30 ? 4.5. ? as-i rece iver.................................................................................................................. ...................... 31 ? 4.6. ? as-i transm itter............................................................................................................... ..................... 31 ? 4.7. ? parameter po rt and pstbn....................................................................................................... ........... 32 ? 4.8. ? data port and dstbn............................................................................................................ ............... 33 ? 4.8.1. ? timing of data i/o and dstbn ................................................................................................... ... 33 ? 4.8.2. ? input data pr e-proces sing...................................................................................................... ....... 34 ? 4.8.3. ? synchronous da ta i/o mode...................................................................................................... .... 35 ? 4.8.4. ? support of 4i/4o signaling in extended addr ess mode ................................................................ 37 ? 4.8.5. ? special functi on of ds tbn ...................................................................................................... ....... 38 ? 4.9. ? data and parameter po rt configuration .......................................................................................... ..... 39 ? 4.10. ? fault indication input pfault .................................................................................................. ........... 40 ? 4.11. ? led out puts .................................................................................................................... ...................... 40 ? 4.11.1. ? slave mode ..................................................................................................................... ............... 40 ? 4.11.2. ? master/repea ter mode ........................................................................................................... ....... 41 ? 4.12. ? oscillator pins osc1, osc2 ..................................................................................................... ........... 42 ? 4.13. ? ic reset....................................................................................................................... ......................... 42 ? 4.13.1. ? power on reset................................................................................................................. ............ 42 ? 4.13.2. ? logic controlled re set......................................................................................................... ........... 43 ? 4.13.3. ? external reset................................................................................................................. ............... 43 ? 4.14. ? uart ........................................................................................................................... ......................... 45 ? 4.15. ? main state machine............................................................................................................. ................. 46 ? 4.16. ? status r egisters ............................................................................................................... .................... 46 ? 4.17. ? communication moni tor/watchdog ................................................................................................. ..... 46 ? 4.18. ? safety mode.................................................................................................................... ...................... 47 ? 4.19. ? master- and re peater mode...................................................................................................... ........... 51 ? 4.19.1. ? master/ repeater mo de activation............................................................................................... .. 51 ? 4.19.2. ? pin assignment ................................................................................................................. ............. 51 ? 4.19.3. ? functional de scription......................................................................................................... ........... 53 ? 4.20. ? write protection of id_code_extension_1........................................................................................ ... 55 ? 5 ? package ou tlines ............................................................................................................... ......................... 60 ? 6 ? package ma rking................................................................................................................ ......................... 61 ? 7 ? ordering in format ion ........................................................................................................... ........................ 62 ?
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 6 of 62 list of figures figure 1 sap5 package pin assignment for the 20 pin version ........................................................................ 13 ? figure 2 sap5 package pin assignment for the 16 pin version ........................................................................ 13 ? figure 3: functional block diagram ................................................................................................................... 14 ? figure 4: data path in master-, repeater- and monitor-mode ............................................................................. 1 ? figure 5: receiver comparator threshold set-up in principle .............................................................................. 31 ? figure 6: timing diagram parameter port p0 ... p3, pstbn ............................................................................. 33 ? figure 7: timing diagram data port d0 ... d3 and dstbn ................................................................................. 34 ? figure 8: principle of delay mode input filt ering (exemplary for slave with address 1) ..................................... 35 ? figure 9: power-on behavior (all modes) .......................................................................................................... 43 ? figure 10: timing diagram external reset via dstbn ....................................................................................... 44 ? figure 11: safety mode data processing ........................................................................................................... 49 ? figure 12: data input voltage constraints in safety mode ................................................................................ 50 ? figure 13: sap package pin assignme nt in master/repeater mode ................................................................ 51 ? figure 14: standard application circuit, direction of data i/o depends on io_code ......................................... 57 ? figure 15: safety mode application .................................................................................................................... 58 ? figure 16: sap5 master mode application ......................................................................................................... 59 ? figure 17: package drawings and dimensio ns for the sop16/sop20-300mil versions .................................. 60 ? figure 18: package marking 20 pin version ....................................................................................................... 61 ? figure 19: package marking 16 pin version ....................................................................................................... 61 ? list of tables table 1: absolute maximum ratings .................................................................................................................... 9 ? table 2: operating conditions ............................................................................................................................ 10 ? table 3: crystal frequency ............................................................................................................................... .1 0 ? table 4: sap5 pin list ............................................................................................................................... ......... 12 ? table 5: assignment of operational modes ........................................................................................................ 16 ? table 6: sap5 master call s and related slave responses .............................................................................. 20 ? table 7: sap5 additional master calls for slave configuration ......................................................................... 21 ? table 8: e2prom read and write times ......................................................................................................... 22 ? table 9: sap5 e2prom - user and firmware area content ............................................................................ 24 ? table 10: sap5 e2prom - user and firmware area programming ................................................................. 25 ? table 11: sap5 e2prom - safety area content .............................................................................................. 26 ? table 12: properties of voltage output pins uout and u5r ............................................................................. 28 ? table 13: as-i bus load properties ................................................................................................................... 29 ? table 14: cdc pin parameters ........................................................................................................................... 29 ? table 15: cut off temperature ........................................................................................................................... 29 ? table 16: dc characteristics of digital high voltage input pins .......................................................................... 30 ? table 17: dc characteristics of digital high voltage output pins ........................................................................ 30 ? table 18: receiver parameters .......................................................................................................................... 31 ? table 19: transmitter current amplitude ........................................................................................................... 31 ? table 20: timing parameter port ....................................................................................................................... 32 ? table 21: timing data port outputs ................................................................................................................... 34 ? table 22: activation of delay mode .................................................................................................................... 35 ? table 23: activation of synchronous mode ........................................................................................................ 36 ? table 24: meaning of master call bits i0 ? i3 in ext_addr_4i/4o_mode .......................................................... 38 ?
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 7 of 62 table 25: data and parameter port configuration for non-safety-mode operation ......................................... 39 ? table 26: data and parameter port configuration in safety mode .................................................................... 40 ? table 27: led status indication .......................................................................................................................... 41 ? table 28: oscillator pin parameters .................................................................................................................... 42 ? table 29: ic initialization times ........................................................................................................................... 42 ? table 30: power on reset threshold voltages ................................................................................................. 42 ? table 31: timing of external reset ...................................................................................................................... 43 ? table 32: status register content ..................................................................................................................... 46 ? table 33: activation of t he sap5 communication watchdog ............................................................................ 47 ? table 34: example for cryptographic code table ............................................................................................. 48 ? table 35: activation of t he sap5 master/repeater mode .................................................................................. 51 ? table 36: sap5 pin assignment in master- and repeater mode ...................................................................... 52 ? table 37: functional distinctions of sap5 master- and repeater mode ........................................................... 53 ? table 38: programmable variation of the loopback time .................................................................................. 53 ? table 39: master/repeater mode parameter ..................................................................................................... 54 ? table 40: write protection of id_code_extension_1 ......................................................................................... 56 ?
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 8 of 62 0 read this first 0.1. important notice products sold by zentrum mikroelektronik dresden ag (z mdi)are covered exclusivel y by the warranty, patent indemnification and other provisions appearing in zent rum mikroelektronik dresden ag standard "terms of sale". zentrum mikroelektronik dresden ag makes no warranty (express, statutory, implied and/or by description), including without limitation any warranties of merchantability and/or fitness for a particular purpose, regarding the information set forth in the ma terials pertaining to zentrum mikroelektronik dresden ag products, or regarding the freedom of any products described in the materials from patent and/or other infringement. zentrum mikroelektronik dresden ag rese rves the right to discontinue production and change specifications and prices of its produ cts at any time and without notice. zentrum mikroelektronik dresden ag products are intended for use in commercial applicatio ns. applications requiring extended temperature range, unusual environmental requirements, or high reliability app lications, such as military, medical life-support or life-sustaining equipment, are spec ifically not recommended without additional mutually agreed upon processing by zentrum mikroelektronik dresden ag for such applications. zentrum mikroelektronik dresden ag reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 0.2. references [1] as-interface complete specification version 3.0, dated 16.09.2004 [2] spezifikation der sicheren as-i-b ertragung, leuze electronic, 12.05.2000 0.3. revision history revision date technical changes page in datasheet b september 2005 first marketed silicon version c march 2007 modified i il ? current range for input low level table 16 at page 30 c march 2007 modified delay mode activation through parameter port p1 page 35 c march 2007 modified synchronous data i/o mode activation through parameter port p2 page 35 c march 2007 modified watchdog activation through parameter port p0 page 46 c march 2007 improved burst protection filter and improved esd behavior d ?
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 9 of 62 1 general device specification 1.1. absolute maximum ratings (non operating) table 1: absolute maximum ratings symbol parameter min max unit note v ltgn voltage reference 0 0 v v ltgp-ltgn voltage difference between ltgp and ltgn (v ltgp - v ltgn ) 0 40 v 1 v ltgp-ltgn_p pulse voltage between ltgp and ltgn (v ltgp - v ltgn ) 0 50 v 2 v inputs1 voltage at pin cdc, d0?d3, p0?p3, dstbn, pstbnbn, led1, led2, pfault, uout -0.3 v uout + 0.3 v v inputs2 voltage at pins osc1, osc2, u5r -0.3 7 v i in input current into any pin except supply pins -50 50 ma 4 h humidity non-condensing 5 v hbm electrostatic discharge ? human body model (hbm2) 1500 v 6 v edm electrostatic discharge ? equipment discharge model (edm) 200 v 7 ? stg storage temperature -55 125 c ? lead soldering temperature sn/pb jedec-j-std-020d 240 c ? lead soldering temperature 100%sn jedec-j-std-020d 260 c r thj-16 thermal resistance of soic 16 package 80 100 k/w 8 r thj-20 thermal resistance of soic 20 package 75 95 k/w 8 1 reverse polarity protection has to be performed externally, 2 pulse with ? 50s, repetition rate ? 0.5 hz 3 v ltgp-ltgn and v ltgp-ltgn_p must not be violated 4 latch-up resistance, reference pin is 0v 5 level 4 according to jedec-020d is guaranteed 6 hbm: c = 100pf charged to v hbm2 with resistor r = 1.5k ? in series, valid for all pins except ltgp-ltgn 7 edm: c = 200pf charged to v edm with no resistor in series, valid for ltgp-ltgn only 8 single layer board, p tot = 0.5w; air velocity = 0m/s ? max. value; air velocity = 2.5m/s ? min. value
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 10 of 62 1.2. operating conditions table 2: operating conditions symbol parameter min max. unit note v ltgn negative supply voltage 0 0 v v ltgp dc voltage at ltgp relating to v ltgn 16 34 v 1, 2 i ltgp operating current at v uin = 30v 6 ma 3 i cl1 max. output sink current at pins d3...d0, dstbn 10 ma i cl2 max. output sink current at pins p0...p3, pstbnbn 10 ma ? amb ambient temperature range, operating range -25 85 c 1 below v ltgpmin the power supply block may not be able to provide the specified output currents at uout and u5r. 2 outside of these limits the send current shape and send current amplitude cannot be guaranteed. 3 f c = 16.000 mhz, no load at any pin, transmitter tu rned off, digital state mach ine is in idle state table 3: crystal frequency symbol parameter nom. unit note f c crystal frequency 5.333/16.000 mhz 4 4 the ic automatically detects whether the crysta l frequency is 5.333mhz or 16.000mhz and controls the internal clock circuit accordingly. 1.3. emc behavior the ic has to fulfill the requirements defined in as-interf ace complete specification v2.11 [1] and related test requirements as-interface slave ics. in addition to the as-interface complete specification and in combination with a reference component circuit the ic has to achieve a communication failure rate less th an 10% of the allowed failure rate according to the "fast transient" test method specified in the re lated as-interface association test procedures. the above specified behavior is correct by design and has to be proven while ic characterization. 1.4. quality standards the quality of the ic will be ensured according to t he zmdi quality standards. zmdi is a qualified supplier according to iso/ts 16949:2002 and iso 14001:1996. the following reference documents ap ply for the development process: management regulation: 0410 product development procedure process specification: zm di c7d 0.6m technology functional device parameters are valid for dev ice operating conditions specified in chapter 1.2 at page 8 . produ ction device tests are performed within the recommended ranges of v ltgp - v ltgn , ? amb = +25c (+85c and -25c on sample base only) unless otherwise stated.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 11 of 62 1.5. failure rate symbol parameter max. unit aql acceptance quality level 0.1 % f55 failure rate at 55c 18 fit f70 failure rate at 70c 60 fit f85 failure rate at 85c 150 fit f125 failure rate at 125c 1400 fit 1.6. humidity class level 3 according to jedec-020d is guaranteed.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 12 of 62 1.7. package pin assignment table 4: sap5 pin list soic 20 pin # soic 16 pin # name direction type description 1 - p1 i/o pull-up/ open drain (*) parameter port p1 / data input port 1 at io-config = 7 2 - p0 i/o pull-up/ open drain (*) parameter port p0 / data input port 0 at io-config = 7 3 1 d1 i/o pull-up/ open drain data port d2 4 2 d0 i/o pull-up/ open drain data port d0 5 3 dstbn i/o pull-up/ open drain data strobe output / reset input 6 4 led1 out open drain led 1 status indication 7 5 osc2 out analog (5v) crystal oscillator 8 6 osc1 in analog/ cmos crystal oscillator / external clock input 9 7 u5r out analog regulated 5v power supply 10 8 ltgn in analog/supply as-i transmitter/receiver output, to be connected to as-i- 11 9 ltgp in analog/supply as-i transmitter/receiver input, to be connected to as- i+ via reverse polarity protection diode 12 10 cdc out analog external buffer capacitor 13 11 uout out analog dec oupled actuator/sensor power supply 14 12 pfault in pull-up periphery fault input (low = periphery fault) 15 13 led2 out open drain led 2 status indication 16 14 pstbnbn i/o pull-up/ open drain parameter strobe output 17 15 d3 i/o pull-up/ open drain data port d3 18 16 d2 i/o pull-up/ open drain data port d2 19 - p3 i/o pull-up/ open drain (*) parameter port p3 / data input port 3 at io-config = 7 20 - p2 i/o pull-up/ open drain (*) parameter port p2 / data input port 2 at io-config = 7 all open drain outputs are nmos based. pull-up properties at input stages are achieved by current sources referring to u5r. (*) the pull-up current source on these parameter ports is switched off if the slave device is programmed with i/o configuration code 7 and a dexg master call is processed.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 13 of 62 dstbn led1 osc2 osc1 p1 p0 d1 d0 p2 p3 d2 d3 pstbn led2 pfault uout u5r ltgn cdc ltgp sap5 pin 1 figure 1 sap5 package pin assignment for the 20 pin version dstbn led1 osc2 osc1 d1 d0 d2 d3 pstbn led2 pfault uout u5r ltgn cdc ltgp sap5 pin1 figure 2 sap5 package pin assignment for the 16 pin version
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 14 of 62 2 basic functional description 2.1. functional block diagram neg transmitter main state machine electronic inductor power supply pos receiver man uart ltgp ltgn cdc u5r p3 ... p0 d3 ... d0 output led2, led1 i / o dstbn output pstbn input pfault dstb led pstb pfault eeprom osc1 osc2 clk c l k oscillator pll c l k offset i / o offset i / o param data uout thermal protection apf power fail detector figure 3: functional block diagram following device functions are associated with the different blocks of the ic: receiver the re ceive block converts the analog telegr am waveform from the as-i bus to a digital pulse coded signal that can be processed further by a digital uart circuit. the receive block is directly connected to the as-i line pins ltgp and ltgn. it converts the differential as-i telegram to a single ended signal and removes the dc offset by high pass filtering. to adapt quickly on changing signal amplitudes in telegrams from different network users, the amplitude of the first telegram pulse is measured by a 3 bit flash adc and the threshold of a positive and a negative comparator is set accordingly to about 50% of the measured level. the comp arators generate the p-pulse and n-pulse signals. transmitter the transmit block transforms a digital resp onse signal to a correctly shaped send current signal which is applied to the as-i bus. du e to the inductive network behavior of the network the changing send current induces voltage pulses on the network line that overlay the dc operating voltage. the voltage pulses shall have sin2-wave shapes. hence, the send current shape must follow the in tegral of the sin2-wave function.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 15 of 62 uart / main state machine / eeprom e2prom write access and other i/o operations of the main state machine are supported in slave mode only (see description of genera l ic operational modes below). in master mode the ic is basically equivalent to a physical layer transceiver. if slave mode is activated, the uart demodulates the received telegrams, verifies telegram syntax and timing and controls a r egister interface to the main state machine. after reception of a correct telegram, the uart generates appropriate receive strobe signals, that tell the main state machine to start further processing. the main state machine decodes the telegram information and starts respective i/o processes or e2prom access. a second register interface is used to send data back to the uart for construction of a telegram response. the uart modulates the response data into a manchester-ii-coded bit stream that is used to control the transmitter unit. electronic inductor the electronic inductor is basically a gyra tor circuit. it provides an inductive behavior between the ic pins ltgp and uout while the inductance is controlled by the capacitor on pin cdc. the inductor decouples the power re gulator of the ic as well as the external load circuit from the as-i bus and hence prev ents cross talk or switching noise from disturbing the telegram communication on the bus. the as-i complete specification describes the input impedance behavior of a slave module by an equivalent circuit that consists of r, l and c in parallel. for example, a slave module in extended address mode sha ll have r > 13.5 kohm, l > 13.5 mh and c < 50pf. the electronic inductor of the sap5 delivers values that are well within the required ranges for output currents up to 55ma (uin>24v). more detailed parameters can be found in chapter 4.1 . the electroni c inductor requir es an external capacitor of 10 f at pin uout for stability. power supply the power supply block consists of a bandgap referenced 5v-regulator as well as other reverence voltage and bias current generators for internal use. the 5v regulator requires an external capacitor at pin u5r of at least 100 nf for stability. it can source up to 4ma for external use, however the power dissipati on and the resulting device heating become a major concern, if too much current is drawn from the regulator. see chapter 4.1 . oscill ator / pll the oscillator supports direct connection of 5.33 mhz or 16.000 mhz crystals with a dedicated load capacity of 12pf and parasitic pin capacities of up to 8pf. the ic automatically detects the oscillation frequency of the connected crystal and controls the internal clock generator circuit accordingly. after power-on reset the ic is set to 16.000 mhz operation by default. after about 200s it will either switch to 5.3 33 mhz operation or remain in the 16.000 mhz mode. the frequency detection is active until the first as-i telegram was successfully received in order to make sure the ic found the correc t clock frequency setting. the detection result is locked thereafter to increase resistance against burst or other interferences. the oscillator unit also contains a clo ck watch dog circuit that can generate an unconditioned ic reset if there was no clock oscillation for more than about 20s. this is to prevent the ic from unpredicted behavio r if no clock signal is available anymore. thermal protection the ic is self protected against thermal ov erload. if the silicon die temperature rises above around 140c for more than 2 seconds, the ic detects thermal overheating, switches off the electronic inductor, performs an ic reset and sets all analog blocks to power down mode. the 5v-regulator is of course also turned off in this state, however, there will still remain a voltage of about 3 ? 3.5v available at u5r that is derived from the internal start circuitry. if the overheat c ondition is left the ic resumes operation and performs an initialization. power fail detector the power fail detector observes the voltage at the as-i-line. it signals at pin pstbn/apf when the voltage drops below ab out 22.5v. active in master mode only. input stage all digital inputs, except of the oscillator pins, have high voltage ca pabilities and pull-up features. for more details see chapters 1.7 , 4.3 , 4.7 , and 4.8 . outp ut stage all digital output stages, except of the oscillator pins, hav e high voltage capabilities and are implemented as nmos open drain buffers. each pin can sink up to 10ma of current. see chapter 4.4 .
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 16 of 62 2.2. general operational modes the sap5 provides two operational modes: slave mode and master/repeater mode. a definition of which operational mode becomes active is made by programming the flag master_mode in the firmware area of the e2prom (see also table 9 on page 24 ). the e2prom is read out at every initialization of the ic. online mode swit ching is not provided. the following configurations apply: table 5: assignment of operational modes selected operational mode master mode flag slave mode 0 master/repeater mode 1 in slave mode the sap5 operates as fully featured as-i slave ic according to as- i complete specification v3.0. in master/repeater mode the sap5 it acts as physical layer tr ansceiver. it translates a digital output signal from the master control logic (etc. plc, p, ?) to a correctly shaped, analog as-i pulse sequence and vice versa. every as-i telegram received is checked for consistency with the as-i communication protocol specifications and if no errors were found, an appropriate receive strobe signal is generated. the following figure shows the different data path configurations. master mode slave mode, asi-channel more detailed signal descriptions can be found in chapters 4.19 master- and repeater mode as well as 4.14 uart . figure 4: dat a path in master-, repeater- and monitor-mode asi- receiver asi- transmitter cmos input led output uart asi+ asi- d0 (tx) led1 (rx) 2.3. slave mode the slave m ode i s the m o st complex operational m ode of the ic. the sap5 does not only support all mandato r y a s -i slave fun c tion s b u t also a va riety of addi tion al fe ature s that e a se s th e de si gn of as-i slave module s . 2.3.1. as- i c o mmunic a tio n c h an ne l the as-i ch a nnel i s di re ctly conn ecte d t o as-i bu s via the pin s lt gp and ltg n . a re ceive r and a tran smi tter unit are con necte d in pa rallel to the pins that allo w fully bi-direction al com m unication throu gh ltg p and ltg n . 2.3.2. paramete r port pins in the 20-pin package the sap5 features a 4-bit wide param eter port and a rel a ted parameter strobe signal pin pstbn. as-i compl e te sp ecification v3 .0 ne wly defi nes a bi dire ct ional m ode f o r p a rameter data. th e s ap5 sup port s this feature that can be a c tivated by spe c ial e2prom setting ( io_code , see chapte r 4.9 ).
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 17 of 62 there is a defined phase relation between a parameter output event, the parameter input sampling and the activation of the pstbn signal. thus it can be used to trigger external logic or a micro controller to process the received parameter data or to provide ne w input data for the as-i slave response. see chapter 4.7 for further details. 2.3.3. data port pins the sap5 provides a 4-bit wide data port. the output s work independently from each other allowing a maximum of 4 output devices to be connected to the sap5 . the directions of the data port pins are set through the io_code , see chapter 4.9 . the d ata port is accompanied by the data strobe signa l dstbn. there is a defined phase relation between a data output event, the input data sampling and the activation of the dstbn signal. thus, it can be used to trigger external logic or a micro controller to proces s the received data or to provide new input data for the as- i slave response. see chapter 4.8 for further details. 2.3.4. data input inversion by default th e logic signal (high / low) that is presen t at the data input pins during the input sampling phase is transferred without modification to the send register , which is interfaced by the uart. by that, the signal becomes directly part of the slave response. some applications work with inverted logic levels. to av oid additional external inverters, the input signal can be inverted by the sap5 before transfer ring it to the send register. the in version of the input signals can be done jointly for all data input pins. see chapter 4.8 . 2.3.5. data input filtering to prevent input signal bouncing fr om being transferred to the as-i master, the data input signals can be digitally filtered. activation of the filter is done jointly either by e2prom configurati on or by the logic state of parameter port pin p2. for more detailed information refer to chapter 4.8 . 2.3.6. synchronous data i/o mode as-i compl ete specification v3.0 newly defines a synch ronous data i/o feature, that allows a number of slaves in the network to switch their outputs at the same time and to have their inputs sampled simultaneously. this feature is especi ally useful if more than 4-bit wide data is to be provided synchronously to an application. the synchronization point was defined to the data exchange event of the slave with the lowest address in the network. this definition relies on the cyclical slave po lling with increasing slave addresses per cycle that is one of the basic communication principles of as-i. the ic always monitors the data communication and detects the change from a higher to a lower slave addr ess. if such a change was recognized, the ic assumes that the slave with the lower address has the lowest address in the network. there are some special procedures that become active during the start of synchronous i/o mode operation and if more than three consecutive telegrams were sent to the same slave address. this is described in more detail in chapter 4.8.3 . 2.3.7. 4 input / 4 output processi ng in extende d address mode a new feature of as-i complete specification v3.0 is also support of 4-bit wide output data in extended address mode. in extended address mode it was, up to co mplete specification v2.11, only possible to send three data output bits from the master to the slave becaus e telegram bit i3 is used to select between a- and b- slave type for extended slave addressing (up to 62 slaves per network) . in normal address mode i3 carries output data for pin d3. the new definition introduces a multiplexed data transfer, so that all 4-bits of the data output port can be used again. a first as-i cycle transfers the data for a 2-bit out put nibble only, while the second as-i cycle transfers the data for the contrary 2-bit nibble. nibble selection is done by the remaining third bit. to ensure continuous alternation of bit information i2 and thus continu ed data transfer to both nibbles, a special watchdog was
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 18 of 62 implemented that observes the state of i2 bit. the watchdog can be activated or deactivated by e2rpom setting. it provides a watchdog filter time of about 327ms. the multiplexed transfer of course increases the refresh time per output by a factor of two, however, some applications can tolerate this increase for the benefit of less external circuitry and better slave address efficiency. the sampling cycle of the data inputs remains unchanged since the meaning of i3 bit was not changed in the slave response with t he definition of the extended address mode. more detailed information is described in chapter 4.8.4 . 2.3.8. as-i safety mode usi ng the sap5 safety mode makes it easy to implement a safety-related as-i slave according to the as-i safety at work concept. slaves complying with the control category 4 according to en 954 ?1 can be implemented even with a minimum of external circuitry. in safety mode the respond of the sap5 ic on a data_exchange master call ( dexg ) is different. instead of responding the regular input data provided at the data por ts, a 4-bit data word from a specific 8*4 bit code table is transmitted to the master. cycling the code table is used to transmit another data word with each dexg master call. the data transmission is supervised by a safety monitor. in safety mode the use of the enhanced data input featur es described above is disabled. in this case the safety mode related inputs act as 3-level inputs. see chapter 4.18 for further details. 2.3.9. enhanced led status indication the sap5 i c supports status indi cation by two led outputs. more detailed information on the signaling scheme can be found in chapter 4.11 . 2.3.10. communication monitor/watchdog data a nd parameter communication are continuously observed by a communication monitor. if neither data_exchange nor write_parameter calls were addressed to and received by the ic within a time frame of about 41ms, a so called no data/parameter exch ange status is detected and signaled at led1. if the respective flags are set in the e2prom the communication monitor can also act as communication watchdog, that initiates a complete ic reset after expiring of the watchdog timer. the watchdog mode can also be activated and deactivated by a signal at parameter port pin p0. for more detailed information see chapter 4.17 . 2.3.11. write protection of id_code_extension_1 as defined in as-i compl ete specification v3 .0 the sap5 also supports write protection for id_code_exten- sion_1 . the feature allows the activation of new manufac turer protected slave profiles and is enabled by e2prom setting. it is described in more detail in chapter 4.20 .
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 19 of 62 2.3.12. summary of master calls in and table 7 on the following pages show the complete set of master calls that are decoded by the sap5 in slave mode. the master calls in table 7 are intended for programming of the ic by the slave manufacturer only. they b ecome deactivated as soon as the lock_ee_prg and safety_program_mode_disable flag are set in the firmware area of the e2prom. as-i complete specification compliance note: in order to achieve full compliance to the as-i complete specification, the program_mode_disable flag must be set by the manufacturer of as-i slave modules duri ng the final manufacturing and configuration process and before an as-i slave device is delivered to field application users.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 20 of 62 table 6: sap 5 master calls and related slave responses master request slave response instruction mne st cb a4 a3 a2 a1 a0 i4 i3 i2 i1 i0 pb eb sb i3 i2 i1 i0 pb eb data exchange dexg 0 0 a4 a3 a2 a1 a0 0 d3 ~sel d2 d1 d0 pb 1 0 d3 d2 d1 d0 pb 1 write parameter wpar 0 0 a4 a3 a2 a1 a0 1 p3 ~sel p2 p1 p0 pb 1 0 p3 p2 p1 p0 pb 1 address assignment adra 0000000a4a3a2a1a0pb1 0011001 write extented id code_1 wid1 01000000id3id2id1id0pb1 0000001 delete address dela 01a4a3a2a1a000 sel000pb1 0000001 reset slave res 0 1 a4a3a2a1a0 1 1 ~sel 100pb1 0011001 read io configuration rdio 0 1 a4 a3 a2 a1 a0 1 0 sel 0 0 0 pb 1 0 io3 io2 io1 io0 pb 1 read id code rdid 0 1 a4 a3 a2 a1 a0 1 0 sel 0 0 1 pb 1 0 id3 id2 id1 id0 pb 1 read id code_1 rid1 0 1 a4 a3 a2 a1 a0 1 0 sel 0 1 0 pb 1 0 id3 id2 id1 id0 pb 1 read id code_2 rid2 0 1 a4 a3 a2 a1 a0 1 0 sel 0 1 1 pb 1 0 id3 id2 id1 id0 pb 1 read status rdst 0 1 a4 a3 a2 a1 a0 1 1 ~sel 1 1 0 pb 1 0 s3 s2 s1 s0 pb 1 broadcast (reset) br01 01111111010111 --- no slave response --- note: in extended address mode the "select bi t" defines whether the a-slave or b-slav e is being addressed. dependent on the typ e of master call the i3 bit carries the select bit information (sel) or the inverted select bit information (~sel). the extended address mode can not be activated, as long as the e2prom flag lock_ee_prg is at logic low level. refer to chapter 3.3 on page 25 for programming the lock _ee_prg flag .
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 21 of 62 master request slave response instruction mne st cb a4 a3 a2 a1 a0 i4 i3 i2 i1 i0 pb eb sb i3 i2 i1 i0 pb eb set id code (rdio)01a4a3a2a1a011000pb1 0011001 set io config (rdid)01a4a3a2a1a011001pb1 0011001 set id code 2 (rid1)01a4a3a2a1a011010pb1 0011001 set control code (rid2)01a4a3a2a1a011011pb1 0011001 set control code 2 (res) 01a4a3a2a1a010100pb1 0011001 enter program mode safet y prgm01000001110111 --- no slave response --- table 7: sap 5 additional master calls for slave configuration
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 22 of 62 3 e2prom 3.1. overview the sap5 provides an on-chip e2prom with typical write and read times according to table 8. table 8: e2p rom read and write times symbol parameter min max. unit note t read_init initialization readout time 50.0 ? s 1 t wrt_adra1 write time after adra master request 38.0 ms 2 t wrt_adra2 write time after adra master request 12.5 ms 3 t wrt_wid1u write time after wid1 master request (user access) 38.0 ms 2 t wrt_wid1m write time after wid1 master request (manufacturer access) 25.0 ms 3 t wrt_prgm single cell write time 12.5 ms 4 1 time includes readout of the conf iguration block. running in safety mode, the user/firmware area and the safety area will be read out in parallel. 2 the lock_ee_prg flag is set 3 the lock_ee_prg flag is not yet set 4 concerns the programming of data in both firmware area and safety area for security reasons the memory area is structured in three independent data blocks and a single configuration block containing the security_flag . the data blocks are named user area, firmware area and safety area. the firmware area contains all manufacturing related configurati on data (i.e. selection of optional features, id codes, ?). it can be protected against undesired data modification by setting the lock_ee_prg flag to ?1?. the user area contains only such data that is relevant for changes at the final application (i.e. field installation of slave module). because the environment where modifications of the user data may become necessary can sometimes be rough and unpredictable, additional securi ty was added to the programming of the user area, ensuring a write access cannot result in an undetected corruption of e2prom data. the safety area contains the cryptogr aphic code table for the safety mode. the e2prom cells in user area, firmware area and safety area have a word width of 6 bit. the sixth bit is not shown in table 9 and table 11 . the sixth bit of each cell represents the odd parity of the respective data word, providing an additional data security mechanism. the programming of the parity bit is performed automatically during the e2prom write process and cannot be influenced by the user. each e2prom read process ? particularly during initialization of the sap5 ? involves an evaluation of the parity bits. in case a wrong parity bit was found in the user area, the entire user area data is treated as corrupted. the ic returns to slave address ?0? and the id_code as well as the io_code are set to 0xf. in case a false parity bit was found in one or more cells of the firmware area or the sa fety area, the status register bit s1 will be set (=?1?), signaling the same state as the input pfault would be set (refer to chapter 4.16 page 46 ).
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 23 of 62 3.2. user area programming user area data can be written by an adra or wid1 master request (refer to table 6 ). any such write access is a ccompanied by two write steps to the security_flag , one before and one after the actual modification of user data. the following procedure is executed when wr iting to the user area of the e2prom: 1. the security_flag is programmed to ?1?. 2. the content of the security_flag is read back, verifying it was programmed to ?1?. 3. the user data is modified. 4. a read back of the written data is performed. 5. if the read back has proven successfu l programming of the user data, the security_flag is programmed back to ?0?. 6. the content of the security_flag is read back, verifying it was programmed to ?0?. successful execution of the e2prom write procedure may be observed at t he status register contents. if bit s0 is set (logic high) the write process is not finis hed yet and the programming data is still volatile. if bit s3 (equals the security_flag ) is set, the write procedure did not succe ssfully complete either because the write cycle was interrupted or due to an internal error. in order to program the data correctly the write request should be repeated. the status register can be read using the as-i master call read_status ( rdst ). in addition to a read out of the data areas, the security_flag of the e2prom is also read and evaluated during ic initialization. in case the value of the security_flag equals ?1? (i.e. due to an undesired interruption of a user area write access), the entire user area data is treated as corrupted. the ic returns to slave address ?0? and the id_code as well as the io_code are set to 0xf. consequently, t he programming of the user area data can be repeated.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 24 of 62 table 9: sap 5 e2prom - user and firmware area content internal e2prom address bit position e2prom cell content description 0 4 ? 0 a4 ? a0 slave address 1 2 ? 0 id1_bit2 ? id1_bit0 id_code_extension_1 (user configurable) 3 id1_bit3 id_code_extension_1 , a/b slave selection in extended address mode 4 not implemented 2 3 ? 0 id1_bit3 ? id1_bit0 id_code_extension_1 (manufacturer configurable) 4 not implemented 3 4 ? 0 not implemented 4 synchronous_data_io synchronized data i/o mode 4 3 ? 0 id_bit3 ? id_bit0 id_code 4 inhibit_write_id1 id_code_extension_1 is manufacturer configurable, refer to page 47 5 3 ? 0 id2_bit3 ? id2_bit0 id_code_extension_2 4 p1_delay_activation if flag is set, the logic value at the parameter pin p1 determines whether the delay_mode function is active or inactive, refer to table 22 6 0 ? 3 io_bit3 ? io_bit0 io_code 4 lock_ee_prg programming of the e2prom firmware region is possible as long as this flag is not set (logic low). 3 delay_mode activates the delay_mode function, refer to table 22 2 invert_data_in all data port inputs are inverted. 1 inhibit_br01 if flag is set, the master call br01 is not executed. 7 0 inhibit_watchdog if flag is set, the watchdog is not activated. 4 p2_sync_activation the synchronized data i/o mode may be activated by parameter bit p2 as described in table 23 on page 36. 3 ext_addr_4i/4o_mode 4 input/ 4 output mode in extended address mode 2 parallel_out_4i/4o enables the parallel data output option in extended address 4i/4o mode 1 master_mode master/repeater mode flag 8 0 p0_watchdog_activation the watchdog can be enabled/disabled by the logic value at the parameter pin p0. 9 10 11 4 ? 0 analogue circuitry trim information user area firmware area
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 25 of 62 3.3. firmware area programming in order to program one of the 5-bit cells of the firm ware area (address 4?8) a special master call according to table 10 must be applied, followed by a dexg or wpar call immediately. write access to the firmware area is possible as long as the lock_ee_prg flag is not set. the write procedure is started after receipt of the dexg / wpar call. finish of write procedure may be observ ed at the status register s0 as described above. the analogue circuitry trim information (address 9?11) c an be written by special test mode operation only. there is no possibility to read out the e2prom data dire ctly. however, as-i-related configuration data like id_code may be read by the respective read_id_code master request. table 10: sap5 e2prom - user and firmware area programming internal e2prom address e2prom cell content programming master calls 0 a4 ? a0 adra master call 1 id1_bit3 ? id1_bit0 2 id1_bit3 ? id1_bit0 wid1 master call 3 not implemented synchronous_data_io i4 4 id_bit3 ? id_bit0 i3 ? i0 set id code (rdio) 1 + dexg/wpar 2 inhibit_write_id1 i4 5 id2_bit3 ? id2_bit0 i3 ? i0 set id code 2 (rid1) 1 + dexg/wpar 2 p1_delay_activation i4 6 io_bit3 ? io_bit0 i3 ? i0 set io config (rdid) 1 + dexg/wpar 2 lock_ee_prg i4 delay_mode i3 invert_data_in i2 inhibit_br01 i1 7 inhibit_watchdog i0 set control code (rid2) 1 + dexg/wpar 2 p2_sync_activation i4 ext_addr_4i/4o_mode i3 parallel_out_4i/4o i2 master_mode i1 8 p0_watchdog_activation i0 set control code 2 (res) 1 + dexg/wpar 2 9 10 11 analogue circuitry trim information accessible by zmdi only 1 according to table 7 2 according to table 6 with information bits corresponding to the left-hand column; dexg if i4= ?0?, wpar if i4=?1?. note: differing from regular wpar / dexg calls, the slave always returns the received data bits i3?i0. user area firmware area
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 26 of 62 3.4. safety area programming the safety area contains the cryptographic code table which consists of 8 data words and one swap-flag each (refer to chapter 4.18 on page 47 for an explanation of the sap5 safety mode). similar to the firmware area it can be protected against undesired data modification by setting the safety_program_mode_ disable flag to ?1?, see table 11 . note : onc e the safety_program_mode_disable flag is set, the safety area of the e2prom is permanently locked, i.e. write access to the safety area as described in chapter 3.4 is possible only as long as the safety_pro gram_mode_disable is set to ?0?. table 11: sap5 e2prom - safety area content logical e2prom address bit position e2prom cell content description 4 s_flag 0 swap flag 0 1 3 ? 0 di_s0 3 ? 0 data input word 0 from safety code table 4 s_flag 1 swap flag 1 2 3 ? 0 di_s1 3 ? 0 data input word 1 from safety code table 4 s_flag 2 swap flag 2 3 3 ? 0 di_s2 3 ? 0 data input word 2 from safety code table 4 s_flag 3 swap flag 3 4 3 ? 0 di_s3 3 ? 0 data input word 3 from safety code table 4 s_flag 4 swap flag 4 5 3 ? 0 di_s4 3 ? 0 data input word 4 from safety code table 4 s_flag 5 swap flag 5 6 3 ? 0 di_s5 3 ? 0 data input word 5 from safety code table 4 s_flag 6 swap flag 6 7 3 ? 0 di_s6 3 ? 0 data input word 6 from safety code table 4 s_flag 7 swap flag 7 8 3 ? 0 di_s7 3 ? 0 data input word 7 from safety code table 1 safety_mode_enable if set, safety mode can be enabled 31 0 safety_program_mode_disable if set, safety area is protected against overriding similar to the firmware area programming, safety area programming is intended to be used only during production set-up of a slave component at the manufact urer?s site. write access to the safety area of the e2prom is feasible in the so called safety program mode . it can be entered only if the safety_program_mode_disable flag is not yet set and if the slave address was set to 0x0. in the case that the slave address equals zero, the reception of the enter_program_mode_safety ( prgm ) call sets the sap5 device into the safety program mode . it should be noted that no response is generated to the enter_program_mode_safety call (refer to as-i complete specification). being in the safety program mode, the write_parameter ( wpar ) and data_exchange ( dexg ) calls are used to transfer data words to the e2 prom similar to the firmware area write procedure described above. however, the address bits a4...a0 of the master telegrams are used to add ress one of the me mory locations of the e2prom (refer to table 11 ). the information bits i4...i0 (normally used for output data) carry the data whi ch shall be stored.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 27 of 62 any wpar or dexg call initializes an autonomous write process with in the ic. the status of the write process can be monitored by evaluating the stat us register of the ic the same way described above. since the ic is still in safety program mode , the address within the read_status master call doesn?t care. in order to execute as many write procedures as desi red, the safety program mode must not be left. however, the sap5 will leave the safety program mode and start it?s initialization procedure if it receives a reset_slave ( res ) master call to any desired slave address. any attempt to access one of the not available e2prom address locations (0, 9 ? 30) through a write_parameter ( wpar ) or data_exchange ( dexg ) command will be ignored. there is no direct read access to the safety area data in safety program mode . an e2prom verification procedure should be carried out e.g. by performing one complete as-i safety cycle (8 dexg calls in minimum 250 ? s intervals) in safety mode operation.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 28 of 62 4 detailed functional description 4.1. power supply the power supply block provides a sens or supply, which is inductively decoupl ed from the as-i bus voltage, at pin uout. the decoupling is realized by an electronic i nductor circuit, which basically consists of a current source and a controlling low pass. the time constant of the low pass that has influence to the resulting input impedance at pin uin, can be adjusted by an external capacitor at pin cdc. a second function of the power supply block is to gener ate a regulated 5v supply for operation of the internal logic and some analog circuitry. the voltage is provided at pin u5r an can be used to supply external circuitry as well, as long as the current requirement s stay within in the specified limits ( table 2 at page 10 ). because the 5v supply is generated out of t he decoupled sensor supply at uout, t he current drawn at u5r has to be subtracted from the total available load current at uout. the power supply dissipates the major amount of power: ptot = v drop * (i uout + i 5v ) + (v uout -5v) * i 5v in total, the power dissipation shall not exceed the specified values of chapter 1.1 . to cope with fast internal and external load changes (spikes) external capacitors at uout and u5r are required. the ltgn pin defines the ground reference voltage for both uout and u5r. 4.1.1. voltage output pins uout and u5r table 12 : properties of voltage output pins uout and u5r symbol parameter min max unit note v uin positive supply voltage for ic operation 16 34 v 1 v drop voltage drop from pin ltgp to pin uout 5.2 7.8 v v uin > 22v 2 v uout uout output supply voltage v uin - v dropmax v uin - v dropmin v i uoutmax v uoutp uout output voltage pulse deviation 1.5 v 3 t uoutp uout output voltage pulse deviation width 2 ms 3 v u5r 5v supply voltage 4.75 5.25 v i uout uout output supply current 0 55 ma i u5r = 0 uin>24v i 5v u5r output supply current 0 4 ma i o total output current i uout + i 5v 60 ma c buout blocking capacitance at uout 10 470 f c b5v blocking capacitance at u5r 100 nf 1 parameter copied from table 2 at page 10 2 the actual voltage drop increases with increasing load current at uout 3 c uout = 10f, output current switches from 0 to i uoutmax and vice versa
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 29 of 62 4.1.2. input impedance (as-i bus load) table 13 : as-i bus load properties symbol parameter min max unit note r in1 equivalent resistor of the ic 13,5 k ? 1,2 l in1 equivalent inductor of the ic 13,5 mh 1,2 c in1 equivalent capacitor of the ic 30 pf 1,2 r in2 equivalent resistor of the ic 13,5 k ? 1,2 l in2 equivalent inductor of the ic 12 13,5 mh 1,2 c in2 equivalent capacitor of the ic 15 + (l-12mh)*10pf/mh pf 1,2 c zener parasitic capacitance of the external over-voltage protection diode (zener diode) 20 pf 1 1 the equivalent circuit of a slave, which is calculated from the impedance of the ic and the paralleled external over-voltage protection diode (zener diode), has to satisfy the requirements of the as-i complete specification for extended address mode slaves. 2 subtracting the maximum parasitic capacitance of the external over voltage protection diode (20pf) either the triple r in1 , l in1 and c in1 or the triple r in2 , l in2 and c in2 has to be reached by t he ic to fulfill the as-i complete specification. table 14: cdc pin parameters symbol parameter min typ max unit note v cdc_in input voltage range -0.3 v u5r v c cdc external decoupling capacitor 100 nf note: a decoupling capacitor defines internal low-pass filter time constant; lower values decrease the impedance but improve the turn-on time. higher values do not improve the impedance but do increase the turn-on time. the turn-on time also depends on the load capacitor at uout. after connecting the slave to the power the capacitor is charged with the maximum current i uout . the impedance will increase when the voltage allows the analog circuitry to fully operate. 4.2. thermal protection the ic continuously observes its silicon die temper ature. if the temperature rises above around 140c for more than 2 seconds the ic will cut off the uout output from the internal voltage reference. thus the current consumption of the ic will drop down to its operating current (refer to table 2 ). in order to prevent an unde sired drawing of transmit current the transmitter is also disabled in case the over temperature cut off condition is true. after over temperature cut off, the output voltage at uout will be restored and the ic performs an initialization if the die temperature has cooled down by 10 ? 20c with an additional time delay of 1s. table 15: cut off temperature symbol parameter min max unit note t cutoff chip temperature for over temperature cut off 125 160 c
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 30 of 62 4.3. dc characteristics ? digital inputs the following pins contain digital high voltage input stages: - input-only pin: pfault - i/o pins: p1, p3, d1, d3, dstbn, pstbn 1 , led1 1 - 3-level i/o pins: p0, p2, d0, d2 3 table 16: dc characteristics of digital high voltage input pins symbol parameter min max unit note v ofl voltage range for input ?offset_low? level 0 1.0 v 3,4 v ofh voltage range for input ?offset_high? level 1.6 v uout v 3,4 v il2 voltage range for input ?low? level 0 2.5 v 4 v ih voltage range for input ?high? level 3.5 v uout v i il current range for input ?low? level -12 -3 a v in = 1v 2 i ih current range for input ?high? level -10 10 a v 0 ? v u5r c dl capacitance at pin dstbn 10 pf 5 1 pstbn and led1 are inputs for test purposes only. 2 the pull-up current is driven by a current source connected to u5r. it stays almost constant for input voltages ranging from 0 to 3.8v. 3 pins p0, p2, d0 and d2 are used as 3-level inputs - i. e. inputs with offset detection - in safety mode only, configuration beyond depends on the slave profile (refer to table 26 on page 40 ) 4 the 3-level input pads contain independent comparator s for the detection of regular input data level and offset. refer to figure 12 on page 50 for constraints to the externally applied voltages in safety mode . 5 the internal pull-up current is sufficient to avoid accid ental triggering of an ic reset if the dstbn pin remains unconnected. for external loads at dstbn a suffi cient pull up resistor is required to ensure v ih ? 3.5v in less than 90ms after the beginning of a dstbn = low pulse. 4.4. dc characteristics ? digital outputs the following pins contain digital high voltage open drain output stages: - output-only pin: led2 - i/o pins: d0 ? d3, p0 ? p3, dstbn, pstbn 1 , led1 1 table 17: dc characteristics of digital high voltage output pins symbol parameter min max. unit note v ol1 voltage range for output ?low? level 0 1 v i ol1 = 10ma v ol2 voltage range for output ?low? level 0 0.4 v i ol2 = 2ma i oh output leakage current -10 10 a v 0h ? v u5r 1 pstbn and led1 are inputs for test purposes only. a slew rate limitation is provided to each digital high voltage output driver which limits the rise and fall times for both high/low and low/high transitions to 40?50ns. note: the rise time for a low/high transition is ma inly influenced by the external pull-up resistor.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 31 of 62 4.5. as-i receiver the receiver detects (telegram) signal s at the as-i line, converts them to digital pulses and forwards them to the uart for further processing. the receiver is in ternally connected between the ltgp and ltgn pins. functional, the receiver removes the dc value of the input signal, band-pass filters the ac signal and extracts the digital output signals from the sin 2 -shaped input pulses by a set of comparators. the amplitude of the first pulse determines the threshold level for all following pulse s. this amplitude is digitally filtered to guarantee stable conditions and to suppr ess burst spikes. this approach combines a fast adaptation to changing signal amplitudes with a high detection safety. the comparators are reset after every detection of a telegram pause at the as-i line. when the receiver is turned on, the transmitter is turned off to reduce the power consumption. table 18: receiver parameters symbol parameter min max unit note v sig ac signal peak-peak amplitude (between ltgp and ltgn) 3 8 v v lsigon receiver comparator threshold level (refer to figure 5 ) 45 55 % related to amplitude of 1st pul se first negative pulse of the as-i telegram v lsigon v lsigon = (0.45 ... 0.55) * v sig / 2 dc level v sig / 2 the ic determines the amplitude of the first negative pulse of the as-i telegram. this amplitude is asserted to be v sig / 2. figure 5: receiver comparator threshold set-up in principle 4.6. as-i transmitter the transmitter draws a modulated current between ltgp and ltgn to generate the communication signals. the shape of the current correspond s to the integral of a sin 2 -function. the transmitter comprises a current dac and a high current driver. the driver requires a sma ll bias current to flow. the bias current is ramped up slowly a certain time before the transmission starts so that any false voltage pulses on the as-i line are avoided. when the transmitter is turned on, the receiver is turned off to reduce the power consumption. the sap5 comprises a clock watchdog that becomes activated once the clock signal is stopped for about 100s ? 150s. thus, the transmitter is prevented from being pe rmanently switched on in case the clock signal is missing. table 19: transmitter current amplitude symbol parameter min max unit note i sig modulated transmitter peak current swing (between ltgp and ltgn) 55 68 ma
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 32 of 62 4.7. parameter port and pstbn the parameter port is always configured for cont inuous bi-directional operation. however, once io_code =0x7 (see table 25 ), the parameter ports will return to high impedance state right after a wpar re quest because they act as data input ports or safety data ports for a following dexg master call. every pin contains an nmos open drain output driver plus a high voltage high impedance digital input stage. received parameter output data is stored at the parame ter output register and subsequently forwarded to the open drain output drivers. a certain time (t pi-latch ) after new output data has arrived at the port, the corresponding inputs are sampled. due to the open drain ch aracter of the output driver, the input value results from a wired and combination of the parameter output value and such signals driven to the port by external sources. the availability of new parameter output data is signaled by the parameter strobe (pstbn) signal as shown in figure 6 . beside s the basic i/o function, the first parameter output event after an ic reset has an additional meaning. it enables the data exchange functionality. any ic reset turns the parameter output register to 0xf and forces the parameter output drivers to high impedance state. simultaneously, a parameter strobe is generated, having the same t setup timing and t pstbn pulse width, as new output data would be driven. table 20: timing parameter port symbol parameter min max unit note t stb output data is valid after pstbn high-low edge 0.0 1.5 s t pstbn pulse width of parameter strobe (pstbn) 6.0 6.8 s 1 t pi-latch acceptance of input data 10.5 12.5 s 2 t p-off parameter port is at high impedance state after pstbn high- low edge 56.0 64.5 s 3 1 the timing of the resulting voltage signal also depends on the external pull up resistor. 2 the parameter input data must be stable within the period defined by min. and max. values of t pi-latch . 3 concerns the io configuration ?7? only
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 33 of 62 pstbn t pi-latch parameter port output data parameter input value (pix) = parameter output value (pox) (wired and with external signal source value) keep stable min max p0..p3 t stb t pstbn t p-off figure 6: timing diagram parameter port p0 ... p3, pstbn 4.8. data port and dstbn 4.8.1. timing of data i/o and dstbn every data pin (d0 ?d3) contains an nmos open drai n output driver as well as a high voltage high impedance input stage. received output data is stored at the data output register and subsequently forwarded to the data pins. a certain time (t di-latch ) after new output data was written to the port the input data is sampled. the availability of new output data is signaled by the data strobe (dstbn) signal as shown in figure 7 . the dstbn pin h as an additional reset input func tion, which is described further in chapter 4.13 ic reset . any ic res et turns the data output register to 0xf and forces the data output drivers to high impedance state. simultaneously, a data strobe is generated, having the same t setup timing and t dstbn pulse width, as new output data would be driven.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 34 of 62 table 21 : timing data port outputs symbol parameter min max unit note t stb output data is valid after dstbn high/low edge 0.0 1.5 s t hold output driver is at high impedance state after dstbn low/high 0.2 1.0 s 1 t dstbn pulse width of data strobe (dstbn) 6.0 6.8 s 2 t di-latch acceptance of input data 10.5 12.5 s 3 1 parameter is only valid if the respecti ve data port is configured as i/o pin. 2 the timing of the resulting voltage signal also depends on the external pull up resistor. 3 the input data must be stable within the period defined by min. and max. values of t di-latch . 4.8.2. input data pre-processing dstbn data port output data d0..d3 keep stable t di-latch min max data port input data t hold t stb t dstbn figure 7: timing diagram data port d0 ... d3 and dstbn beside s the standard input function the data port offers different data pre-processing features that can be activated by setting corresponding flags in the firmware area of the e2prom. ? input inverting the input values of all four dat a input channels are inverted if the invert_data_in flag is set. ? input delay if the delay mode is activated, a new input value is returned to the master if equal input data was sampled for two consecutive data_exchange cycles. as long as the condition is no t true, previous valid data is returned. to suppress undesired input data validation in case of immediately repeated data_exchange calls (i. e. as-i masters immediately repeat one data_exchange requests if no valid slave response was received on the first request) input data sampling is blocked for 256s (-6.25%) after every sampling event.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 35 of 62 the filter output of each d ata port is pres et to ?0? after reset or as long as the data_exchange_disable flag is set, respectively. input signal filter output sampling point figure 8: principle of delay mode input f iltering (exemplary for slave with address 1) > 256 s (-6.25%) dexchg addr 1 dexchg addr1 dexchg addr 1 slave slave slave activation of delay mo de depends on the e2prom flags delay_mode and p1_delay_activation and the value of the parameter port p1 ou tput register as shown in table 22 . delay mode cannot be activated when safety mode is e nabled. note: the input signal at parameter port p1 does not influence activation of input delay mode at all. only the master can change the activation status by sending a corresponding write_parameter (wpar) request. table 22: activation of delay mode delay_mode p1_delay_activation parameter p1 output register delay mode 0 x x off 1 0 x on 1 1 1 off 1 1 0 on 4.8.3. synchronous data i/o mode since th e slaves in an as-i network are called succ essively by the master, the data input and output operations of different slaves are not synchronized norma lly. if there is, however, an application that requests accurate synchronized data i/o timing, the respecti ve slaves may be operated in the synchronous mode. concerning the communication with the master, slaves running in the synchronous mode behave like regular slaves. however, the input data sampling as well as the output data driving is determined by the polling cycle of the respective as-i network as described below. activation of the sap5 synchronous m ode is related to the e2prom flags synchronous_data_io and p2_sync_activation (refer to table 9 ) and the value of the parameter port p2 output register as follows: note: the input signal at parameter port p2 does not influence activation of synchronous data i/o mode at all. only the master can change the ac tivation status by sending a corresponding write_parameter (wpar) request.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 36 of 62 table 23: activation of synchronous mode synchronous_data_io p2_sync_activation parameter p2 ouput register synchronous mode 0 x x off 1 0 x on 1 1 1 off 1 1 0 on note: the synchronous mode is not available if safety mode is enabled. with activated synchronous mode, input data sampling as well as output data driving events are moved to different times synchronized to the polling cycle of the as-i net work. nevertheless, the communication principles between master and slave remain unchanged compared to regular operation. following rules apply: ? data i/o is triggered by the dexg call to slave with the lowest slave address in the network. based on the fact, that a master is calling slaves successively with rising slave addresses, the sap5 considers the trigger condition true, if t he slave address of a received dexg call is less than the slave address of the previous (correctly received) dexg call. data i/o is only triggered, if the slave has (correct ly) received data during the last cycle. if the slave did not receive data (i.e. due to a communication error) the data outputs are not changed and no data strobe is generated (arm+fire principle). the in puts however, are always sampled at the trigger event. ? if the slave with the lowest address in the network is operated in the synchronous mode , it postpones the output event for the received data for a fu ll as-i cycle. this is to keep all output data of a particular cycle image together. note: to make this feature useful, the master sha ll generate a data output cycle image once before the start of every as-i cycle. the image is derived from the input data of the previous cycle(s) and other control events. once an as-i cycle has started, the image shall not change anymore. if a- and b- slaves are installed in parallel at one address, the master shall address all a-slaves in one cycle and all b-slaves in the other cycle. the input data, sampled at the slave with the lowest slave address in the network, is sent back to the master without any delay. thus, the input data cy cle image is fully captured at the end of an as-i cycle, just as in networks without any synchronous mode slaves. in other words, the input data sampling point has simply moved to the beginn ing of the as-i cycle for all synchronous mode slaves. ? if the synchronous data io mode is enabled through eeprom setting ( synchronous_data_io = ?1?, p2_sync_activation = ?0?), the first dexg call that is received by a particular slave after the activation of the data port ( data_exchange_disable flag was cleared by a wpar call) is processed like in regular operation. this is to capture decent input dat a for the first slave response and to activate the outputs as fast as possible. the data i/o operation is repeated toget her with the i/o cycle of the other synchronous mode slaves in the network at the common trigger event. by that, the particular slave has fully reached the synchronous mode. ? if the p2_sync_activation flag is set to ?1? the synchronous data io mode can be activated or deactivated during normal operation by sending write_parameter calls containing the appropriate value in p2 (see table 23 ). if the p2 output regi ster changes from ?1? to ?0? the synchronous data io mode gets enabled in the first instance. real synchronous dat a i/o operation is reached after reception of the next dexg call addressing the slave and the occurrence of the common trig ger event. as in standard operation (synchronous data io mode is ac tivated by eeprom setting) the firs t dexg still processes a data io operation immediately. this is to capture decent input data for the slav e response and to activate the outputs as fast as possible.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 37 of 62 the data i/o operation is repeated toget her with the i/o cycle of the other synchronous mode slaves in the network at the common trigger event. by that, the particular slave has fully reached the synchronous mode. if the p2 output register changes from ?0? to ?1? the synchronous data io mode gets deactivated and disabled immediately. in case a synchronous data i/o event was already scheduled but not yet processed (armed but no fired) before the synchro nous data i/o mode beca me deactivated, the associated data output value gets lost. reactivation of the synchronous data i/o mode oc curs in same manner as described above if p2 changes back to ?0?. ? to avoid a general suppression of data i/o in the special case that a slave in synchronous mode receives dexg calls only to its own address (i.e. employment of a handheld programming device), the synchronous mode becomes deactivated, onc e the sap5 receives three consecutive dexg calls to its own slave address. the ic resumes to synchronous mode operation after it observed a dexg call to a different slave address then its own. the reactivation of the synchronous mode is handled likewise for the first dexg call after activation of t he data port or after activation of the synchronous data i/o mode by p2 changing to ?0? (see description above). if any of the data ports d0..d3 is conf igured as pure output (named out in table 25 ), the sap5 returns the output data t hat was received from the master immediately back in its slav e response. since there is no input function available at such port, the return value is independent from a possible synchronous mode operation . running in synchronous mode , the sap5 generates the data strobe (d stbn) signal as well, whereas the timing of input sampling and output buffering exactly corresponds to the regular operation (refer to figure 7 and table 21 ). 4.8.4. support of 4i/4o signaling in extended address mode in extended addre ss mode the information bit i3 of the as-i master telegram is used to distinguish between a- and b-slaves that operate in parallel at the same as-i sl ave address. for more detailed information refer to [1] as-i complete specification. besides the benefit of an increased address range, th e cycle time per slave is increased in extended address mode from 5 ms to 10 ms and the us eable output data is reduced from 4 to 3 bits. because of the later, extended address mode slaves can usually control a maximum of 3 data outputs only. the input data transmission is not effected since the slave response still carries 4 data information bits in extended address mode. additionally, the sap5 supports applications that requ ire 4 bit wide output data in extended address mode, but can tolerate further increased cycle times (i.e. push buttons and pilot lights). such applications shall be directly characterized by a new slave profile 7.a.x.7 that is to be defined in the as-i complete specification. if the ic is operated in extended address mode and the ext_addr_4i/4o_mode flag is set (=?1?) in the e2prom (refer to table 9 ) it treats information bit i2 as sele ctor fo r two 2-bit wide data output banks: o bank_1 = d0/d1 o bank_2 = d2/d3 . a master shall consecutively transmit data to bank_1 and bank_2 , toggling the information bit i2 in the respective master calls. however, the sap5 triggers a data output event (modification of the data output ports and generation of data strobe) as follows: o if the parallel_out_4i/4o flag is set (=?1?) in the e2prom (refer to table 9 ) the sap5 triggers a data outp ut event only if information bit i2 is equal to ?0?. by that, new output data is issued at the data port synchronously for both banks at the same time. o if the parallel_out_4i/4o flag is not set (=?0?) the sap5 tr iggers a data output event at every cycle. however, depending on the information bit i2 only one bank of the data port gets refreshed.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 38 of 62 following coding applies: table 24: meaning of master call bits i0 ? i3 in ext_addr_4i/4o_mode operation / meaning parallel_out_4i/4o = ?0? parallel_out_4i/4o = ?1? master call bit i2 = ?0? i2 = ?1? i2 = ?0? i2 = ?1? i0 i1 d2 = i0 d3 = i1 d1 = unchanged d0 = unchanged d2 = unchanged d3 = unchanged d1 = i1 d0 = i0 d2 = i0 d3 = i1 d1 = do1_tmp 2 d0 = do0_tmp 2 d2 = unchanged 1 d3 = unchanged 1 d1 = unchanged 1 d0 = unchanged 1 do1_tmp = i1 do0_tmp = i0 i2 i2: /sel-bit for transmission to bank_1 (d0/d1) / bank_2 (d2/d3) i3 i3: /sel-bit for a-slave/b-slave addressing notes: 1 if i2 = ?1? then i0/i1 are directed to temporary data output registers do0_tmp / do1_tmp 2 if i2 = ?0? then i0/i1 are directed to the data output registers d2/d3 and do0_tmp / do1_tmp are directed to the data output registers d0/d1 in order to ensure that both bank_1 and bank_2 data are refreshed continuously, the sap5 supervises the alternation of the i2 sel-bit by use of the 4i/4o watchdog. the 4i/4o watchdog gets activated as soon as ? the communication watchdog is activated (refer to table 33 ). ? the ic is operated in extended address mode and the ext_addr_4i/4o_mode flag is set (=?1?) in the e2prom. ? slave address is unequal to zero (0). ? no e2prom write access is active. ? the slave is activated, i.e. the data_exchange_disable flag is cleared. if there is no alternation of the i2 bit for more than 327ms (+16ms) ms after the activation of the slave the 4i/4o watchdog takes the following actions: ? it generates data and parameter strobe signals at the dstbn an pstbn pins with timing according to figure 6 and figure 7 . ? after dstbn an pstbn strobe generation finished , the 4i/4o watchdog invokes an unconditioned ic reset. it sets the data_exchange_disable flag and - afterwards - starts the ic initialization procedure, switching all data and parameter outputs inactive. input data is captured and returned to the master at ever y cycle, independent of the value of information bit i2 4.8.5. special function of dstbn beside its standard output function the data strobe pi n serves as external reset input for all operational modes of the ic. pulling the dstbn pin low for more than a minimum reset time generates an unconditioned reset of the ic, which is immediately followed by an in itialization of the state ma chine (e2prom read out). further information on the ic reset behavior, especially in regard to the signal timing, can be found at chapter 4.13 ic reset .
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 39 of 62 4.9. data and parameter port configuration data and parameter ports are configured by programming the io_code in the e2prom. moreover, the configuration also depends on the safety_mode_enable settings. note : below table 25 refers to slaves not ru nning in safety mode (refer to chapter 4.18 ) the followi ng configurations are possible: ? out : output only, data are valid up to the next dstbn/pstbn strobe pulse ? in : input only, open drain output is fixed at high-impedance state ? i/o : bi-directional port with timing according to figure 6 and figure 7 ? inout : in c ase io_code = 7 parameter ports are configured outputs after wpar master calls and inputs after dexg master calls, respectively. ? passiv : no input function and open drain output is fixed at high-impedance state if one of the data ports d0?d3 is configured as out, the sap5 slave answer to a dexg master request contains the respective information bit i0...i3 received from the master. however, parameter ports p0...p3 are always operated bi-directional, including a read-back of the actual port level as described in chapter 4.8 on page 33 . table 25 : data and parameter port configuration for non-safety-mode operation io_code d0 d1 d2 d3 1 p0 p1 p2 p3 1 0 in in in in out out out out 1 in in in out out out out out 2 in in in i/o out out out out 3 in in out out out out out out 4 in in i/o i/o out out out out 5 in out out out out out out out 6 in i/o i/o i/o out out out out 7 2 out out out out inout inout inout inout 8 out out out out out out out out 9 out out out in out out out out a out out out i/o out out out out b out out in in out out out out c out out i/o i/o out out out out d out in in in out out out out e out i/o i/o i/o out out out out f 3 passiv passiv passiv passiv out out out out 1 slaves running in extended_address_mode ( id_code = 0xa) will output the respective select bit (i3) at the p3 pin and at the d3 pin in case it is configured as out or i/o. 2 the special case io_code = 0x7 causes the parameter ports acting as data inputs after dexg master calls. thus a bi-directional data exchange with separate data inputs and outputs is possible. parameter ports are always outputs after wpar master calls. note: io_code = 0x7 is not allowed for the sap5 16 pin version. 3 there is no data exchange possible in case io_code = 0xf, i.e. data outputs are always at high impedance state, no slave answer is generated for received dexg master calls.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 40 of 62 table 26: data and parameter port configuration in safety mode package version io_code d0 d1 d2 d3 p0 p1 p2 p3 1 16 pin 0?6, 8?f f-d0* in d0* out f-d2* in d2* out don?t care don?t care don?t care don?t care 16 pin 7 1 don?t care don?t care don?t care don?t care don?t care don?t care don?t care don?t care 20 pin 0?6, 8?f f-d0* in d0* out f-d2* in d2* out p0 out p1 out p2 out p3 out 20 pin 7 2 d0 out d1 out d2 out d3 out f-d0* in p0 out d0* out p1 out f-d2* in p2 out d2* out p3 out 1 io_code = 0x7 is not allowed for the sap5 16 pin version. 2 parameter ports are parameter outputs during wpar master calls and after dexg master calls. they are in high impedance state after wpar master calls and act as input when a dexg master calls is performed. 4.10. fault indication input pfault the fault indication input pfault is provided for s ensing a periphery fault-messaging signal. it contains a high voltage high impedance input stage that sets the status bit s1 of the as-i slave to ?1? if it detects a low level at the pfault pin. dc properties of the pin are specified at table 16 . signal tran sitions at the pfault pin become visible in s1 with a slight delay, bec ause a clock synchronizing circuit is located in between. 4.11. led outputs 4.11.1. slave mode the sap5 provides two led pins fo r enhanced stat us indication. led1 and led2 both comprise nmos open drain output drivers. in addition, le d2 contains a high voltage high impeda nce input stage for purposes of the ic production test. in order to comply with the signaling schemes defined in the as-i complete specification a red led shall be connected to led2 and a green led shall be connected to led1 . following status indication is supported
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 41 of 62 table 27 : led status indication priority / status led1 / led 2 note 1. power off no power supply available gree n red 2. external reset dstrbn driven low for more than 90ms. 3. periphery fault alternating periphery fault signal generated at pfault input. 4. no data exchange (address = 0) slave is waiting for address assignment. data port communication is not possible. 5. no data exchange the ic was reset by the c ommunication watchdog or by res or br01 master calls, thus the data_exchange_disable flag is still set, prohibiting data port communication. ic is waiting for a write_parameter request. 1 6. normal operation data communication is established red green red green red green red red red red red 1 this status is not signaled if the communicati on watchdog is not activa ted (refer to chapter 4.17 communication monitor/watchdog ). the flashi ng frequency of any flashing status indication is 2 ? 3 hz . in case of the simultaneous occurrence of several states the status with the highest priority is signaled. 4.11.2. master/repeater mode in ma ster/repeater mode led1 provides the manchester-ii-coded, re-syn chronized equivalent of the telegram signal received at the as-i input channel. every received as-i telegram is checked for consistency with the protocol specifications and timing jitters become removed as long as they stay within the specified limit s. in case a telegram error is detected, the output becomes inactive for a certain time periode, see chapter 4.19.3 . led2 is al ways logic high (high impedance) in master /repeater. in such applications, the green led shall be connected to pin uout or different supply levels.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 42 of 62 4.12. oscillator pins osc1, osc2 table 28: oscillator pin parameters symbol parameter min max unit note v osc_in input voltage range -0.3 v u5r v c osc external parasitic capacitor at o scillator pins osc1, osc2 0 8 pf c crystal crystal load capacitance 0 12 pf v il input ?low? voltage 0 1.5 v 1 v ih input ?high? voltage 3.5 v u5r v 1 1 for external clock applied to osc1 the oscillator supports direct connecti on of 5.33 mhz or 16.000 mhz crystals with a dedicated load capacity of 12pf and parasitic pin capacities of up to 8pf. the ic automatically detects the oscillation frequency of the connected crystal and controls the inte rnal clock generator circuit accordingl y. the oscillator unit also contains a clock watch dog circuit that can generate an unconditioned ic reset if there was no clock oscillation for more than about 20s. this is to prevent the ic from unpred icted behavior if no clock signal is available anymore. 4.13. ic reset any ic reset turns the data output and parameter output registers to 0xf and forces the corresponding output drivers to high impedance st ate. except at power on reset, data strobe and parameter strobe signals are simultaneously generated to visualize possibl y changed output data to external circuitry. the data_exchange_disable flag becomes set during ic reset, prohibiting any data port activity right after ic initialization and as long as the external circuitry was not pre-conditioned by de cent parameter output data. consequently the as-i master has to send a write_parameter call in advance of the first data_exchange request to an initialized slave. following ic initialization times apply: table 29: ic initialization times symbol parameter min max unit note t init initialization time after software reset (generated by master calls reset_slave or broadcast_reset ) or external reset via dstbn 2 ms 1 t init2 initialization time after power on 30 ms 2 t init3 initialization time after power on with high capacitive load 1000 ms 3 1 guaranteed by design 2 ?power on? starts latest at v uin = 18v, external capacitor at pin uout less than or equal 10f 3 c uout = 470f, t init3 is guaranteed by design only 4.13.1. power on reset in ord er to force the ic into a defined state after power up and to avoid uncontrolled switching of the digital logic if the 5v supply (u5r) breaks do wn below a certain minimum level, a power on reset is executed under the following conditions: table 30: power on reset threshold voltages symbol parameter min max unit note v por1f v u5r voltage to trigger internal rese t procedure, falling voltage 1.2 1.7 v 1 v por1r v u5r voltage to trigger init procedure, rising voltage 3.5 4.3 v 1 t low power-on reset pulse width 4 6 s 1 guaranteed by design
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 43 of 62 uin u5r t low reset about 15v v por1f v por1r figure 9: power-on behavior (all modes) note: the power-on reset circuit has a threshold voltage reference. this reference matches the process tolerance of the logic levels and must not be very accurate. all values depend slightly on the raise and fall time of the supply voltage. 4.13.2. logic controlled reset the ic al so becomes reset after reception of reset_slave or broadcast_reset commands, expiration of the (enabled) communication watchdog or entering of a fo rbidden state machine state (i.e. due to heavy emi). 4.13.3. external reset the ic can be reset externally by pulling the dstbn pin low for more than a minimum reset time. the external reset input function is provided in every operational mode of the ic ? slave mode and master/repeater mode . the following signal timings apply: table 31: timing of external reset symbol parameter min max unit note t noreset dstbn low time for no reset initiation 90 ms t reset reset execution time, dstbn h/l transition to hi-z out put drives at do0...do3, p0?p3 99 ms t init state machine initialization time after reset (e2prom read out) 2 ms
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 44 of 62 dsr do0..do3 t noreset t reset t init hi-z po0..po3 hi-z data port output data parameter port output data external reset the external reset is generated ?edge sensitive? to the expiration of the t reset timer. the initialization procedure is starting immediately after the event, indepen dent of the state of dstbn. the external reset state lasts if dstbn still remains low after t reset + t init . the corresponding error state display is described in chapter 4.11. figure 10 : timing diagram external reset via dstbn
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 45 of 62 4.14. uart the uart performs a syntactical and timing wise analysis of the received telegrams at the as-i input channel. it converts the pulse coded as-i input signal into a m anchester-ii-coded bit stream and provides the receive register with decoded telegram bits. the uart also r ealizes the manchester-ii-co ding of a slave answer. in master/repeater mode the output si gnal of the manchester coder (as-i pulse to man signal conversion) is resynchronized and forwarded to pin led1. any pulse ti ming jitters of the received as-i signal become removed, as long as they stay within the specified maximum limits. if the received as-i telegram does not pass one of the different error checks (see detailed des cription below), the led1 output the output becomes inactive for a certain time periode, see chapter 4.19.3 . the comp arator stages at the as-i-line rece iver generate two pulse-coded output signals ( p_pulse , n_pulse ) disjoining the positive and negative telegram pulses for further processing. to reduce uart sensitivity on erroneous spike pulses, pu lse filters suppress any p_pulse , n_pulse activity of less than 750 ns width. after filtering, the p_pulse and n_pulse signals are checked in accordance with the as-i complete specification for following telegram transmission errors: start_bit_error the initial pulse following a pause must have negative polarity. violation of this rule is detected as start_bit_error . the first pulse is the reference for bit decoding. the first bit detected shall be of the value 0. alternating_error two consecutive pulses must have different pol arity. violation of this rule is detected as alternating_error . note: a negative pulse shall be followed by a positive pulse and vice versa. timing_error within any master request or slave response, the digita l pulses that are generated by the receiver are checked to start in periods of after the start of the initial neg ative pulse, where n = 1 ... 26 for a master request and n = 1 ... 12 for a slave response. violation of this rule is detected as timing_error. s s sn ? ? ? 500.1 875.0 )3*( ? ? note: there is a certain pulse timing jitter associated with the receiver output signals (compared to the analog signal waveform) due to sampling and offset effects at the comparator stages. in order to take the jitter effects into account, the timing tolerance specifications differ slightly from the definitions of the as-i complete specification. no_information_error derived from the manchester-ii-coding rule , either a positive or negative pulse shall be detected in periods of after the start of the initial negative pulse, whe re n = 1 ... 13 for a master request and n = 1 ... 6 for a slave response. violation of this rule is detected as no_information_error . s s sn ? ? ? 500.1 875.0 )6*( ? ? note: the timing specification relates to the re ceiver comparator output signals. there is a certain pulse timing jitter in the digi tal output signals (compared to the analog signal waveform) due to sampling and offset effects at the comparator stages. in order to take the jitter effects into account, the ti ming tolerance specificat ions differ slightly from the definitions of the as-i complete specification. parity_error the sum of all information bits in master requests or slave responses (excluding start and end bits, including parity bit) must be even. violation of this rule is detected as parity_error. end_bit_error the pulse to be detected after the start pulse shall be of positive polarity, whe re n = 13 (78 ? s) for a master request and n = 6 (36 ? s) for a slave response. violation of this rule shall be detected as an end_bit_error. s s sn ? ? ? 500.1 875.0 )6*( ? ? note: this stop pulse shall finish a master request or slave response. length_error telegram length supervision is processed as follows. if during the first bit time after the end pulse of a master request (equivalent to the 15 th bit time) for synchronized slaves (during the first three bit times for not synchronized slaves, equivalent to the bit times 15 to 17) or during the first bit time after the end pulse of a slave response (equivalent to the 8 th bit time) a signal different from a pause is detected, a length_error is detected.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 46 of 62 if at least one of these erro rs occurs, the received tel egram is treated invalid. in this case, the uart will not generate a receive strobe signal. it moves to asynchr onous state and wait for a pause at the as-i line input. after a pause was detected, the uart is ready to receive the next telegram. receive strobe signals are generally used to validate the correctness of the received data. receive strobe starts the internal processing of a master request. if the uart was in asynchronous state before the signal was generated, it transforms to synchronous state thereafter. in case the received slave address matches the stored address of the ic, the transmitter is turned on by the receive strobe pulse, letting the output driver settle smoothly at the operation point (a voiding false pulses at the as-i line). 4.15. main state machine the main state machine controls the overall behavior of the ic. depending on the configuration data stored in the e2prom, the state machine activates one of the diffe rent ic operational modes and controls the digital i/o ports accordingly. in slave mode it processes th e received master telegrams and computes the contents of the slave answe r, if required. table 6 on page 20 lists all master calls that are decoded by the sap5 in slave mode. to preve nt the critical situation in which t he ic gets locked in a not allo wed state (i.e. by imission of strong electromagnetic radiation) a nd thereby could jeopardize the entire system, all prohibited states of the state machine will lead to an unconditioned logic rese t which is comparable to the as-i call ?reset slave (res)?. 4.16. status registers table 32 shows the sap5 status register c ontent. the use of status bits s0, s1 and s3 is compliant to the as- interface complete specification. status bit s2 is not used. the status register content can be determined by use of a read_status (rdst) master request (refer to table 6 ). table 32 : status register content status register bit sx = 0 sx = 1 s0 e 2 prom write accessible slave address stored volatile and/or e 2 prom access blocked (write in progress) 1 s1 no periphery fault detected, (input pfault = ?1?), e 2 prom firmware area and safety area content consistent periphery fault detected, (input pfault = ?0?), parity bit error in e 2 prom firmware area or safety area s2 static zero n/a s3 e 2 prom content consistent e 2 prom contains corrupted data 1 status bit s0 is set to ?1? as soon as a dela master request was received and the slave address was unequal to ?0? before. additionally, it is set for the entire duration of each e 2 prom write access. 4.17. communication monitor/watchdog the ic contains an independent communication monitor that observes the processing of data_exchange ( dexg ) and write_parameter ( wpar ) requests. if no such requests have been processed for more than 94.2ms (+4ms) the communication monitor recognizes a no data/parameter exchange status and turns the red status led (led2) on. any following data_exchange or write_parameter request will let the communication monitor start over and turn the red status led off. the communication monitor is only activated at slav e addresses unequal to zero (0) and while the ic is processing the first write_parameter request after initialization. it becom es deactivated at any ic reset or after the reception of a delete_address request. activation of the communication watchdog depends on several e2prom flags and the parameter port p0 output register
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 47 of 62 note: the value of the parameter port p0 input does not influence the watchdog activation at all. only the master can change the activation st atus by sending a corresponding write_parameter (wpar) request. this allows using the feature even if io-code 7 is selected. in this case, the parameter port pins are mapped into data input pins. but since the activation of the co mmunication watchdog only depends on the value of the parameter output register, the watchdog function ality still remains cont rolled by the master. watchdog activation through the value of paramete r port p0 is not available in safety mode. table 33: activation of the sap5 communication watchdog lock_ee_prg e2prom flag inhibit_watchdog e2prom flag p0_watchdog_activation e2prom flag safety_mode _enable parameter port p0 output reg watchdog activation 0 x x x x off 1 1 x x x off 1 0 0 x x on 1 0 1 1 x on 1 0 1 0 0 off 1 0 1 0 1 on the communication watchdog recognizes a no data exchange status as soon as the following conditions come true together: ? the communication watchdog is activated. ? no dexg or wpar request was processed for more than 94.2ms (+4ms). ? slave address is unequal to zero (0). ? no e2prom write access is active. if the communication watchdog detects a no data exchange status, it takes the following actions: ? it concurrently generates data and parameter strobe signals at the dstbn an pstbn pins with timing according to figure 6 and figure 7 . note: at this time, the data and parameter output values still c omply with the values received with the last dexg and wpar master call, respectively. ? after dstbn an pstbn strobe generation finished, the communication watchdog invokes an unconditioned ic reset. it sets the data_exchange_disable flag and - afterwards - starts the ic initialization procedure, switching all data and parameter outputs inactive. in order to resume to normal data port communication after a watchdog ic reset , the data_exchange_disable flag must be cleared again. theref ore, the master has to send a wpar request again before data port communication can be reestablished. this ensures new parameter setup of possibly connected external circuitry. the state until the data_exchange_disable flag returns to ?0? is signaled by a certain led1 and led2 status indication (refer to 4.11 ). 4.18. safety mode using the sap5 safety mode makes it easy to implement a safety-related as-i slave according to the as-i safety at work concept. slaves complying with the control category 4 according to en 954 ?1 can be implemented even with a minimum of external circuitry. the safety mode is active as soon as the e2prom flag safety_mode_enable is set to ?1? (logic high). thus, it is basically independent on the slav e profile, whereas the assignment of the 3-level-input pins mentioned below to either the data- or the parameter port depends on the io_code as described in table 26 on page 40 .
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 48 of 62 furthermore, in order to fulfill certain security require ments, the safety mode is not combinable with one or more of the following sap5 features: ? delay mode (chapter 4.8.2 ) ? synchrono us mode (chapter 4.8.3 ) ? ext_addr_4i/4o_mo de (chapter 4.8.4 ) ? p0 watchdog activation (chapter 4.17 ) the safety m ode of the sap5 ic is of relevance to the actions following an dexg master request. instead of the regular input data provided at the data ports, a 4-bit data word from a specific 8 * 4 bit code table as described in [2] is transmitted to the master. cycling t he code table is used to transmit another data word with each dexg master call. in order to meet certain safety requirements the data words transmitted to the master pass through a special pre-processing. therefore, the c ode table stored within the safety area of the e2prom (refer to table 11 on page 26 ) does not match the reference code table as specif ie d in [2] but is derived from a special coding scheme as described below. table 34: example for cryptographic code table reference code table step 1 cycle d0/d2 by one cycle step 2 invert d0/d2 step 3 : swap d1 ? d3 code table written to the e2prom d3 d2 d1 d0 d3 d2 d1 d0 d3 d2* d1 d0* d3* d2* d1* d0* swap_flag 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 1 1 0 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 0 0 1 1 0 0 1 0 1 1 1 0 1 0 1 1 1 1 1 0 1 1 1 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 the e2prom code table has to be derived from a refe rence code table which meets the requirements of [2] as follows: 1. looking up to the reference code table, the data bit vectors d0 and d2 are scrolled forward by one cycle. refer to table 34 for an example. 2. data bit vectors d0 and d2 are inverted and stored as d0* and d2* in the e2prom. 3. four out of eight data bits from the vector d1 are interchanged with the respective data bits from vector d3. the respective bits are marked with swap_flag = ?1?. unchanged data bit pairs are marked with swap_flag = ?0?. coded in such a way, the vect ors are stored as d1* and d3* in the e2prom . 4. the additional swap_flag attached to each data word is stored in the e2prom as well. running in safety mode, the e2prom data bits d0* and d2* are put out at the port d1/d3 or p1/p3, respectively (for port configuration refer to table 26 on page 40 ). an external circuit has to invert these sign als, it adds a voltage offset (refer to figure 12 ) and delays it for about 20 ? s. thus the data actually will be transmitted with the following as-i cycle. furthermore, the safety-related switches are connected between the external circuitry and the sap5 safety inputs f-d0* and f-d2* (refer to figure 11 ).
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 49 of 62 d2* f-d2* d0* inverting, offset1, delay inverting, offset2, delay f-d0* swap_flag i2 as-interface communication i0 i3 i1 d1* d3* offset2 f-d3* offset1 sap5 f-d1* information stored in the e 2 prom figure 11: safety mode data processing the sp ecial input ports f-d0* and f-d2* act as 3-level-i nput pins in safety mode. in order to ensure proper decoding of input data, the voltages must sa tisfy requirements as specified in below figure 12 and table 16 on pag e 30 , respectively.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 50 of 62 offset d0/d2 low level d0/d2 high level v ofl min (0.0v) v ofl max (1.0v) v ofh = v il2 min (1.6v) v ofh = v il2 max (2.5v) v ih min (3.5v) v uout figure 12: data input voltage constraints in safety mode as soon as the f-d0* input pad detects an offset level less than v ofl (max) the sap5 resets the data input for d1 (f-d1*), signalling an open state at the safety switch connected to d0 *. the input data for d3 (f-d3*) will be reset if the f-d2* detects an offset level less than v ofl (max), respectively. provided that the offset levels are not missing, the e 2 prom bits d1* and d3* are transmitted as data bits d1 and d3 if swap_flag = ?0?, otherwise they are swapped. in order to avoid desynchronization with the sa fety monitor in case the as-i master repeats a dexg call, the sap5 will not update the data code word for 224 ? s (+16 ? s) after a dexg call had been processed.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 51 of 62 4.19. master- and repeater mode 4.19.1. master/ repeater mode activation the sap5 m aster/ repeater mode functionality gets enabled by use of the e2prom flag master_mode (refer to table 9 ). in order to activate the master_mo de , an ic reset (refer to chapter 4.13 on page 42 ) has to be perfo rmed after programming of the e2prom master_mode flag. for distinction between mast er- and repeater mode the id_code may be set to a certain value as described in table 35 . note : the id_code ha s to be programmed before activation of the master_mode flag. once the master_mode flag is set to logic high, the slave functionality of the sap5 is no longer available, preventing any write access to the e2prom by use of as-i master requests as described on page 25 . more over, the master- and repeater mode functionalit y may be disabled generally by use of a hidden e2prom flag. this flag is inaccessible by the us er, but may be set during the zmdi production test. table 35: activation of the sap5 master/repeater mode master_mode e2prom flag id_code master mode 1 master mode 2 repeater mode 0 x off off off 1 0?4 on off off 1 6?0xf off on off 1 5 off off on 4.19.2. pin assignment in master- and repeater m ode the sap5 pins are configured as follows. pins which ar e not used are kept at logic high (high impedance) state in order to reduce internal power dissipation of the ic. resetn rx _ dat osc2 osc1 not used not used not used tx _ dat not used not used not used not used a pf not used not used uout u5r ltgn cdc ltgp sap5 pin 1 figure 13: sap package pin assignment in master/repeater mode
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 52 of 62 table 36: sap5 pin assignment in master- and repeater mode signal name pin configuration soic 20 pin # soic 16 pin # name in master/repeater mode description 1 - p1 none i/o not used 2 - p0 none i/o not used 3 1 d1 none i/o not used 4 2 d0 tx_dat in transmit signal (manchester ii signal) 5 3 dstbn resetn in external reset input (active low) 6 4 led1 rx_dat out receive signal (manchester ii signal) 7 5 osc2 osc2 out crystal oscillator 8 6 osc1 osc1 in crystal oscillator / external clock input 9 7 u5r u5r out regulated 5v power supply 10 8 ltgn ltgn in as-i transmitter/receiver output, to be connected to as-i- 11 9 ltgp ltgp in as-i transmitter/receiver input, to be connected to as-i+ via reverse polarity protection diode, input for the power fail comparator 12 10 cdc cdc out external buffer capacitor 13 11 uout uout out decoupl ed actuator/sensor power supply 14 12 pfault none in not used 15 13 led2 none out not used 16 14 pstbn apf out as-i power fail signal 17 15 d3 none i/o not used 18 16 d2 none i/o not used 19 - p3 none i/o not used 20 - p2 none i/o not used
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 53 of 62 4.19.3. functional description in master/repeater mode the sap5 provides a simple physical-layer interface function between the as-i line and an external binary channel . the signal rx_dat represents the manchester-ii-coded, re-synchronized equivalent of the telegram signal received at the as-i input channel. polarity of that bitstream depends on the programmed operation mode according to table 37 . table 37 : functional distinctions of sap5 master- and repeater mode modulation of signal rx_dat in case of asi power fail loopback mode polarity of signal rx_dat master mode 1 on on active high master mode 2 off on active high repeater mode off off active low every received as-i telegram is checked for consistency with the protocol specifications and timing jitters become removed as long as they stay within the specified limit s. in case a telegram error is detected, the output signal becomes inactive for a time period defined by t break (refer to table 39 ). the sig nal tx_dat is directly forwarded to the as-i line transmitter avoiding any additional logic delays. in case the loopback mode is not active, the as-i receiver gets di sabled as long as the sap5 is transmitting an as-i signal. otherwise, the transmitted signal is re ad back in parallel and provided at the rx_dat output for checkup purposes. the loopback time t loopback is mainly defined by the analog signal pr ocessing within the receiver and the transmitter. however, an additional delay of up to 1875ns may be inserted if necessary. therefore, the id _code_extension_2 eeprom register has to be programmed as described below. note : the id_code_extension_2 has to be programmed before programming of the master_mode flag. once the master_mode flag is set to logic high, the slave func tionality of the sap5 is no longer available, preventing any write access to the e2prom by use of as-i master requests as described on page 25. table 38 : programmable variation of the loopback time id_code_extension_2 (id2_bit3 ? id2_bit0) ? t loopback unit 0000 0 0001 +125 0010 +250 0011 +375 0100 +500 0101 +625 0110 +750 0111 +875 1000 +1000 1001 +1125 1010 +1250 1011 +1375 1100 +1500 1101 +1625 1110 +1750 1111 +1875 ns
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 54 of 62 in master/repeater mode the sap5 prov ides an as-i power-fail detector. it co nsists of a comparator directly connected to the ltgp pin which generates a logic sign al in case the voltage at the ltgp pin drops below v apf (refer to table 39 ). a subsequent digital signal processing of the comparator output signal is performed as follows: ? an anti-bouncing filter removes each signal states shorter than 6 ? s. this is to eliminate the influence of as-i telegrams which are added onto the as-i dc voltage. ? an additional anti-bouncing filter with different f ilter times for activation and deactivation of the power- fail signal removes short power-fail pulses. ? the as-i power-fail signal is provided directly active high as signal apf. ? additionally, in master mode , the as-i power-fail signal modulate s the rx_dat signal, whereas the active state is signaled by logic high level. table 39: master/repeater mode parameter symbol parameter min max unit note t loopback loopback time in master mode 4.9 6.5 ? s 1 v apf as-i power fail voltage threshold 21. 5 23. 5 v ? t apf_rx_dat minimum activation time for signaling of as-i power fail by use of the rx_dat signal 640 704 ? s 2 t apf_on_rx_dat release time of the as-i power fail state within the rx_dat signal 64 ? s 2 t apf_apf minimum activation time for signaling of as-i power fail by use of the apf signal 704 768 ? s 2 t hold_apf as-i power fail hold time 64 ? s t apf_off delay time after return of the as-i power 64 128 ? s t break break time in case of an erroneous as-i signal 9 15 ? s 1 loopback time is the time difference between an edge in the man code of signal tx_dat and the corresponding edge in the manchester -code of the signal rx_dat. the voltage trigger level for measurement of the edge time is defined by v u5r /2. the actual loopback time may be adjusted by programming the id_code_extension_2 eeprom register as described in table 38 . 2 in master mode, the as-i power fail state is alread y signaled by the rx_dat signal as soon as the power fail condition is true for a time more than t apf_rx_dat. however, in order to start the apf minimum hold state (t hold_apf ), the power fail condition must remain true for another time period defined by t apf_on_rx_dat . otherwise, the rx_dat signal returns to its idle state (logic low) immediately.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 55 of 62 4.20. write protection of id_code_extension_1 the id_code_extension_1 register of the sap5 can either be manufact urer configurable or user configurable. as soon as the lock_ee_prg flag is set, access to the id_code_extension_1 is handled as follows: ? if the flag inhibit_write_id1 is set (?1?) in the firmware area of the e2prom, id_code_extension_1 is manufacturer configurable (refer to table 9 ). in this ca se the slave response to a read_id_code_1 ( rid1 ) request is constructed out of the data stored on the internal e2prom address 2 in user area of the e2prom. it doesn?t matter which data is stored in the id_code_extension_1 register in e2prom address 1 in the user area. the ic will always respond with the protected ma nufacturer programmed value. there is one exception to this principle. if the ic is operated in extended address mode, bit3 of the returned slave response is taken from the e2prom address 1 register in the user area. this is because bit 3 functions as a/b slave selector bit in this case and must remain user configurable. to ensure consistency of id_code_extension_1 stored in the data image of master as well as in the e2prom of the slave, the sap5 will not process a write_extended_id_code_1 request if the data sent does not match the data that is stored in protected part of the id_code_extension_1 register. it will neither access the e2prom nor send a slave response in this case. note: as defined in the as-i complete specification [1] a modification of the a/b slave selector bit must be performed bit selective. that means the as-i master must read the id_code_extension_1 first, modify bit3 and send the new 4 bit word that consists of the modified bit3 and the unmodified bits 2?0 back to the slave. ? if the inhibit_write_id1 flag is not set (?0?), id_code_extension_1 is completely user configurable. the data to construct the slave response to a read_id_code_1 request is completely taken from the id_code_extension_1 register on e2prom address 1 in the user area. a write_extended_id_code_1 request will always be answered an d initiate an e2prom write access procedure in this case. manufacturer configuration of the id_code_extension_1 register is only possible as long as the lock_ee_prg flag is not yet set. in this case, the write_extended_id_code_1 requ e st causes a write access that differs from the procedure described on page 22 . instead of the sec urity_flag procedure, the id_code_extension_1 is written to both e2prom addresses 1 and 2 in the user area of the e2prom. this way of duplicate saving ensures data consistency even in the case of an accidental interruption of the e2prom write process during modification of bit3 in extended address mode . refer to table 40 for an overview a bout the different programming and readout options of id_code_extension_1.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 56 of 62 table 40: write protection of id_code_extension_1 master call id_code lock_ee_prg inhibit_write_id1 reaction slave answer 0 write id1_user + id1_manufacturer (user area address 1 and 2) yes new id1 matches id1_manufacturer : write id1_user + id1_manufacturer yes 0 1 new id1 does not match id1_manufacturer : no action no 0 write id1_user yes new id1 matches id1_manufacturer : write id1_user yes ? 0xa 1 1 new id1 does not match id1_manufacturer : no action no 0 write id1_user + id1_manufacturer yes new id1[2:0] matches id1_manufacturer [2:0]: write id1_user + id1_manufacturer yes 0 1 new id1[2:0] does not match id1_manufacturer [2:0]: no action no 0 write id1_user yes new id1[2:0] matches id1_manufacturer [2:0]: write id1_user yes wid1 0xa 1 1 new id1[2:0] does not match id1_manufacturer [2:0]: no action no 0 return id1_user 0 1 return id1_manufacturer 0 return id1_user ? 0xa 1 1 return id1_manufacturer 0 return id1_user 0 1 return id1_user [3], id1_manufacturer [2:0] 0 return id1_user rid1 0xa 1 1 return id1_user [3], id1_manufacturer [2:0] yes the slave answer to a write_id_code1 requ e st is ?0? in any ca se as specified in table 6
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 57 of 62 applicatio n circuits the following figures show typical application cases of the sap5. please note that these schematics show only principle circuit drafts. for more detailed application information see the separate sap5 application notes document. figure 14 outlines a standard slave appli cation circuit compliant to the first as-i ic. figure 15 shows an safety mode appli cation circuit. a master mode application is shown in figure 16 . cdc ltgp osc1 os c2 u5r ltgn uout p3 p2 p1 p0 d3 d2 d1 d0 pstbn dstbn pfault led1 led2 green red a si+ a si - p3 p2 p1 p0 pstbn d 3 d 2 d1 d0 dstbn pfault 24v 0v 100n 100n 10 ? figure 14: standard application circui t, direction of data i/o depends on io_code
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 58 of 62 cdc ltgp osc1 osc2 u5r ltgn uout d2 d3 d0 asi+ asi- 100n 100n 10 ? d1 r1 r2 r3 c1 figure 15: safety mode application r1 and c1 form a low-pass-filt er for the delay of the output of the sap5 ic for about 20 ? s. the transistor performs the inversion, the voltage divider r2/r3 shift the low level to 1.5v ? 2.5v. the high level is provided from the pin?s pull-up feature.
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 59 of 62 cdc ltgp os c1 os c2 u5r ltgn uout p3 p2 p1 p0 d3 d2 d1 d0 / tx_dat pstbn / apf dstbn / resetn pfault led2 led1 / rx_d at asi+ asi - 10 0n 100n 10 ? vdd vdd ou t gnd vdd ou t gnd vdd out gnd vdd out gnd / power fail receive (man-code output of the recieved asi signal) / reset transmit (man-code input for the a si sig n al) gnd figure 16: sap5 master mode application
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 60 of 62 5 package outlines the ic is packaged in a 20 pin sop20-300mil package ( figure 17 ) or in a 16 pin sop16-300mil package ( figure 17 ). figure 17: package drawings and dimensions for the sop16/sop20-300mil versions
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 61 of 62 6 package marking pin 1 top view bottom view pin 1 llllll ppppp-a zmdi d - xxxxyzz + g1 figure 18: package marking 20 pin version pin 1 top view bottom view pin 1 llllll + p pppp-b zmdi d - xxxxyzz g1 figure 19: package marking 16 pin version top marking: ppppp-a produ ct name sop20 package ppppp-b product name sop16 package zmdi manufacturer d- revision code xxxx date code (year and week) y assembly location zz traceability bottom marking: llllll zmdi lot number
sap5s / sap51 universal actuator-sensor interface ic data sheet july 17, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 3.1 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is preliminary and subject to changes without notice. 62 of 62 7 ordering information ordering code operating temperature range package type rohs conform packaging minimum order quantity sap5sd-a-g1-t 1) sap51d-a-g1-t 2) -25c to +85c sop20 / 300 mil y tubes (37 parts/tube) 370 pcs. (10 tubes) sap5sd-a-g1-r 1) SAP51D-A-G1-R 2) -25c to +85c sop20 / 300 mil y tape & reel (1000 parts/reel) 1000 pcs. (one reel) sap5sd-b-g1-t 1) sap51d-b-g1-t 2) -25c to +85c sop16 / 300 mil y tubes (46 parts/tube) 460 pcs. (10 tubes) sap5sd-b-g1-r 1) sap51d-b-g1-r 2) -25c to +85c sop16 / 300 mil y tape & reel (1000 parts/reel) 1000 pcs. (one reel) 1) full safety mode: full featured sap5 ic, no ic functions are blocked by e2prom programming. ic is user programmable to operate in slave mode, master mode and safety mode 2) without safety mode: sap5 ic with functional compliance to sap4 .1 ic + features according to as-i complete spec v3.0. as-i safety option is disabled by an e2prom flag that is not accessible for users . example: sap5 sap5sd-a-g1-t design revision: d: 3rd revision* package type: 14: sop14 16: sop16 delivery form: t: tube r: ta p e & reel product version: s: safety 1: standard package material: g1: ?green? plastic package with lead-free terminals , p ure sn * current design revision; other design revisions are currently not available. not all product versions are available - please see the next page or ask zmdi for the required ones. for the current revision of this document and for additional product information please look at www.zmdi.com. sales and further information www.zmdi.com asi@zmdi.com zentrum mikroelektronik dresden ag grenzstrasse 28 01109 dresden germany zmd america, inc. 1525 mccarthy blvd., #212 milpitas, ca 95035-7453 usa zentrum mikroelektronik dresden ag, japan office 2nd floor, shinbashi tokyu bldg. 4-21-3, shinbashi, minato-ku tokyo, 105-0004 japan zmd far east, ltd. 3f, no. 51, sec. 2, keelung road 11052 taipei taiwan zentrum mikroelektronik dresden ag, korean office posco centre building west tower, 11th floor 892 daechi, 4-dong, kangnam-gu seoul, 135-777 korea phone +49.351.8822.7274 fax +49.351.8822.87274 phone +855-ask-zmdi (+855.275.9634) phone +81.3.6895.7410 fax +81.3.6895.7301 phone +886.2.2377.8189 fax +886.2.2377.8199 phone +82.2.559.0660 fax +82.2.559.0700 disclaimer : this information applies to a product under development. its characteristics and specifications are subject to change without notice. zentrum mikroelektronik dresden ag (zmd ag) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. the information furnished he reby is believed to be true and accurate. however, under no circumstances shall zmd ag be liable to any customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. zmd ag hereby ex pressly disclaims any liability of zmd ag to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of zmd ag for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise.
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